Abstract: This device for quantization of an analogue signal, called the input signal, includes an electronic circuit, called the sign analysis circuit (110), designed to supply a first bit of the output signal, called the sign signal (Bs) which takes a first value when the input signal (Ve) is positive and a second value when the input signal (Ve) is negative. It includes in addition an electronic circuit, called the envelope analysis circuit (112), designed to supply a second bit of the output signal called the envelope variation bit (Bvar env), which takes a first value, called high value, when an envelope signal (Venv) of the input signal is increasing, and a second value, called low value, when the envelope signal (Venv) is decreasing.

Abstract: A signals reception chain including: an input interface receiving a signal and transforming the received signal into at least two signals correlated in phase or in opposite phase, each of the correlated signals being distributed on at least one channel, the channels being identical, at least one analog-digital converter that operates on 1 bit of the signals in phase or in opposite phase, on each of the channels, and a digital processor for processing the converted signals stemmed from the channels, and performing operations between the converted signals in phase or in opposite phase.

Abstract: The invention relates to an N-bit asynchronous Quantizer including a 2N?1 signal amplifier stages (G12-G2N?12) arranged in series, the input of the first stage being capable of receiving a signal to be quantized; 2N?1 comparators (C12-C2N?12), one comparator being connected to the output of each amplifier stage (G12-G2N?12), and capable of comparing the value of this output with a predetermined threshold value; and at least 2N?2 delay lines (D12-D2N?12) placed at the output of the 2N?2 first comparators, the signals supplied at the output of the delay lines (D12-D2N?12) and of the last comparator constituting at any instant the quantized binary values of the input signal with a time shift.

Abstract: Transmitter device which includes at least: a) one delay line designed to output M signals which are delayed in relation to each other, where M is an integer greater than 1; b) a memory, designed to store at least M digital samples of a waveform, where each digital sample contains N bits, and to output each of the M digital samples successively on N output lines respectively under the control of one of the M delayed signals; and c) a digital-analog converter which includes N inputs linked to N output lines, designed to convert the M digital samples received as input from the N output lines of the memory and to successively output, on an output of the digital-analog converter, each of the M analog converted digital samples which together form an analog signal which is representative of the waveform.

Abstract: This invention relates to a signals reception chain comprising: an input interface receiving a signal and transforming the received signal into at least two signals correlated in phase or in opposite phase, each of the correlated signals being distributed on at least one channel, analog-digital conversion means on at least 1 bit of the correlated signals, on each of the channels, digital processing means of the converted signals comprising at least means of performing operation between said converted signals.