Patents by Inventor David LeVine

David LeVine has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12646873
    Abstract: A dense, high-speed interconnection may be formed with a mating header and receptacle connector. The header connector may have groups of mating contact portions extending from the connector housing. Structural projections may extend from the housing adjacent some or all of the groups of mating contact portions. The groups of mating contact portions may be signal and ground mating contact portions associated with a signal pair. The groups may be arranged in an array and the structural projections may be arranged in an array intercalated with the array of the groups of mating contact portions. A receptacle connector may include an array of apertures configured to receive the structural projections. The structural projections may be shaped and positioned to reduce damage to the mating contact portions of the header connector, enable reliable manufacture, and to provide a high-density mating interface.
    Type: Grant
    Filed: December 9, 2022
    Date of Patent: June 2, 2026
    Assignee: Amphenol Corporation
    Inventors: Marc B. Cartier, Jr., John Robert Dunham, Mark W. Gailus, John Pitten, David Levine, Vysakh Sivarajan
  • Patent number: 12613095
    Abstract: A system and method for position detection. A method includes identifying a plurality of stationary periods based on a plurality of sample groupings including a plurality of acceleration values, wherein each stationary period is a sample grouping of the plurality of sample groupings having an acceleration magnitude value below a threshold, wherein each sample grouping includes a subset of samples from among a plurality of samples of sensor data; determining a plurality of velocity values by integrating a portion of the plurality of acceleration values, wherein the portion of the plurality of acceleration values which is integrated in order to determine the plurality of velocity values excludes the plurality of stationary periods; and determining a plurality of positions by integrating at least a portion of the plurality of velocity values.
    Type: Grant
    Filed: May 5, 2025
    Date of Patent: April 28, 2026
    Assignee: The Joan and Irwin Jacobs Technion-Cornell Institute
    Inventor: David Levine
  • Publication number: 20260039039
    Abstract: An electrical interconnect for passing high speed signals through an electronic system with a high density of signals and high signal integrity. The interconnect includes an electrical connector and a transition portion of a printed circuit board to which the connector is mounted. Signal conductors are connected to pads on the surface of the PCB using edge-to-pad mounting. The pads align with intermediate portions of the signal conductors such that transitions within the connector that could degrade signal integrity are avoided. The signal conductors may be positioned as individually shielded broadside coupled pairs extending in rows within the connector. Surface traces on the PCB connect the pads to signal vias aligned for vertical routing out of the connector footprint. Ground planes underlying the surface traces facilitate a transition from the signal paths in the connector to those in the PCB with low mode conversion avoiding resonances in the connector shields.
    Type: Application
    Filed: October 8, 2025
    Publication date: February 5, 2026
    Applicant: Amphenol Corporation
    Inventors: John Robert Dunham, Marc B. Cartier, JR., Mark W. Gailus, David Levine, Allan Astbury, Vysakh Sivarajan, Daniel B. Provencher, Eric Leo
  • Publication number: 20250344316
    Abstract: A printed circuit board includes a plurality of layers including attachment layers and routing layers; and via patterns formed in the plurality of layers, each of the via patterns including first and second signal vias forming a differential signal pair, the first and second signal vias extending through at least the attachment layers; ground vias extending through at least the attachment layers, the ground vias including ground conductors; and shadow vias located adjacent to each of the first and second signal vias, wherein the shadow vias are free of conductive material in the attachment layers. The printed circuit board may further include slot vias extending through the attachment layers and located between via patterns.
    Type: Application
    Filed: May 20, 2025
    Publication date: November 6, 2025
    Applicant: Amphenol Corporation
    Inventors: Mark W. Gailus, Marc B. Cartier, JR., Vysakh Sivarajan, David Levine
  • Publication number: 20250329967
    Abstract: A modular electrical connector with broad-side coupled signal conductors in a right angle intermediate portion. Broadside coupling provides balanced pairs for very high frequency operation. The connector may be assembled with multiple subassemblies, each of which may have multiple pairs of signal conductors. The subassemblies may be formed from an insulative portion having grooves in opposite sides into which the intermediate portions of signal conductors. Covers, holding the signal conductors in the grooves, may establish the position of the signal conductors relative to reference conductors at the exterior of subassembly, so as to provide a controlled impedance. Lossy material may be positioned between the pairs in a subassembly and/or may contact the reference conductors of the subassemblies, and the lossy material of the subassemblies may in turn be connected with a conductive structure.
    Type: Application
    Filed: May 9, 2025
    Publication date: October 23, 2025
    Applicant: Amphenol Corporation
    Inventors: Marc B. Cartier, JR., John Robert Dunham, Mark W. Gailus, Donald A. Girard, JR., Brian Kirk, David Levine, Vysakh Sivarajan
  • Patent number: 12444863
    Abstract: An electrical interconnect for passing high speed signals through an electronic system with a high density of signals and high signal integrity. The interconnect includes an electrical connector and a transition portion of a printed circuit board to which the connector is mounted. Signal conductors are connected to pads on the surface of the PCB using edge-to-pad mounting. The pads align with intermediate portions of the signal conductors such that transitions within the connector that could degrade signal integrity are avoided. The signal conductors may be positioned as individually shielded broadside coupled pairs extending in rows within the connector. Surface traces on the PCB connect the pads to signal vias aligned for vertical routing out of the connector footprint. Ground planes underlying the surface traces facilitate a transition from the signal paths in the connector to those in the PCB with low mode conversion avoiding resonances in the connector shields.
    Type: Grant
    Filed: April 24, 2023
    Date of Patent: October 14, 2025
    Assignee: Amphenol Corporation
    Inventors: John Robert Dunham, Marc B. Cartier, Jr., Mark W. Gailus, David Levine, Allan Astbury, Vysakh Sivarajan, Daniel B. Provencher, Eric Leo
  • Publication number: 20250294669
    Abstract: Described herein are mounting interfaces for electrical connectors capable of supporting high speed signals and having high density, including up to 70 GHz and higher. Some embodiments provide a connector footprint for a substrate having a pair of signal contact pads on a surface of the substrate and a pair of connecting traces that are interior to the substrate and electrically couple the signal contact pads to a first pair of signal vias (e.g., to a routing layer of the substrate). In some embodiments, a second pair of signal vias may electrically couple the signal contact pads to the connecting traces interior to the substrate. In some embodiments, a portion of a ground layer of the substrate may separate the signal contact pads in the pair. Mounting interfaces described herein enable operation at high frequencies without resonances or other degradation of signal integrity.
    Type: Application
    Filed: March 10, 2025
    Publication date: September 18, 2025
    Applicant: Amphenol Corporation
    Inventors: Paul Galvin, David Levine, Marc B. Catier, JR., Mark W. Gailus, Vysakh Sivarajan
  • Patent number: 12300942
    Abstract: A modular electrical connector with broad-side coupled signal conductors in a right angle intermediate portion. Broadside coupling provides balanced pairs for very high frequency operation. The connector is assembled with multiple subassemblies, each of which has multiple pairs of signal conductors. The subassemblies are formed from an insulative portion having grooves in opposite sides into which the intermediate portions of signal conductors. Covers, holding the signal conductors in the grooves, establish the position of the signal conductors relative to reference conductors at the exterior of subassembly, so as to provide a controlled impedance. Lossy material is positioned between the pairs in a subassembly and/or contacts the reference conductors of the subassemblies, and the lossy material of the subassemblies is in turn connected with a conductive structure.
    Type: Grant
    Filed: May 12, 2023
    Date of Patent: May 13, 2025
    Assignee: Amphenol Corporation
    Inventors: Marc B. Cartier, Jr., John Robert Dunham, Mark W. Gailus, Donald A. Girard, Jr., Brian Kirk, David Levine, Vysakh Sivarajan
  • Publication number: 20250024602
    Abstract: A printed circuit board includes: a plurality of layers including attachment layers and routing layers; and via patterns formed in one or more of the plurality of layers, each of the via patterns including: first and second signal vias configured to accept contact tails of signal conductors of a connector; ground vias configured to accept contact tails of ground conductors of the connector; ground shadow vias located adjacent to each of the first and second signal vias; and non-plated holes located between each of the ground shadow vias and the signal vias. Different layers of the plurality of layers may have different antipad configurations.
    Type: Application
    Filed: July 8, 2024
    Publication date: January 16, 2025
    Applicant: Amphenol Corporation
    Inventors: Marc B. Cartier, Jr., Mark W. Gailus, David Levine, Vysakh Sivarajan
  • Publication number: 20240196518
    Abstract: A printed circuit board includes a plurality of layers including attachment layers and routing layers; and via patterns formed in the plurality of layers, each of the via patterns including first and second signal vias forming a differential signal pair, the first and second signal vias extending through at least the attachment layers; ground vias extending through at least the attachment layers, the ground vias including ground conductors; and shadow vias located adjacent to each of the first and second signal vias, wherein the shadow vias are free of conductive material in the attachment layers. The printed circuit board may further include slot vias extending through the attachment layers and located between via patterns.
    Type: Application
    Filed: February 21, 2024
    Publication date: June 13, 2024
    Applicant: Amphenol Corporation
    Inventors: Mark W. Gailus, Marc B. Cartier, JR., Vysakh Sivarajan, David Levine
  • Patent number: 11950356
    Abstract: A printed circuit board includes a plurality of layers including attachment layers and routing layers; and via patterns formed in the plurality of layers, each of the via patterns including first and second signal vias forming a differential signal pair, the first and second signal vias extending through at least the attachment layers; ground vias extending through at least the attachment layers, the ground vias including ground conductors; and shadow vias located adjacent to each of the first and second signal vias, wherein the shadow vias are free of conductive material in the attachment layers. The printed circuit board may further include slot vias extending through the attachment layers and located between via patterns.
    Type: Grant
    Filed: December 13, 2022
    Date of Patent: April 2, 2024
    Assignee: Amphenol Corporation
    Inventors: Mark W. Gailus, Marc B. Cartier, Jr., Vysakh Sivarajan, David Levine
  • Publication number: 20240014609
    Abstract: A modular electrical connector with broad-side coupled signal conductors in a right angle intermediate portion. Broadside coupling provides balanced pairs for very high frequency operation. The connector may be assembled with multiple subassemblies, each of which may have multiple pairs of signal conductors. The subassemblies may be formed from an insulative portion having grooves in opposite sides into which the intermediate portions of signal conductors. Covers, holding the signal conductors in the grooves, may establish the position of the signal conductors relative to reference conductors at the exterior of subassembly, so as to provide a controlled impedance. Lossy material may be positioned between the pairs in a subassembly and/or may contact the reference conductors of the subassemblies, and the lossy material of the subassemblies may in turn be connected with a conductive structure.
    Type: Application
    Filed: May 12, 2023
    Publication date: January 11, 2024
    Inventors: Marc B. Cartier, JR., John Robert Dunham, Mark W. Gailus, Donald A. Girard, JR., Brian Kirk, David Levine, Vysakh Sivarajan
  • Publication number: 20230420874
    Abstract: An electrical interconnect for passing high speed signals through an electronic system with a high density of signals and high signal integrity. The interconnect includes an electrical connector and a transition portion of a printed circuit board to which the connector is mounted. Signal conductors are connected to pads on the surface of the PCB using edge-to-pad mounting. The pads align with intermediate portions of the signal conductors such that transitions within the connector that could degrade signal integrity are avoided. The signal conductors may be positioned as individually shielded broadside coupled pairs extending in rows within the connector. Surface traces on the PCB connect the pads to signal vias aligned for vertical routing out of the connector footprint. Ground planes underlying the surface traces facilitate a transition from the signal paths in the connector to those in the PCB with low mode conversion avoiding resonances in the connector shields.
    Type: Application
    Filed: April 24, 2023
    Publication date: December 28, 2023
    Applicant: Amphenol Corporation
    Inventors: John Robert Dunham, Marc B. Cartier, JR., Mark W. Gailus, David Levine, Allan Astbury, Vysakh Sivarajan, Daniel B. Provencher, Eric Leo
  • Patent number: D1002551
    Type: Grant
    Filed: March 4, 2022
    Date of Patent: October 24, 2023
    Assignee: Amphenol Corporation
    Inventors: Marc B. Cartier, Jr., Mark W. Gailus, David Levine, Vysakh Sivarajan, John Robert Dunham, John Pitten
  • Patent number: D1002552
    Type: Grant
    Filed: April 25, 2022
    Date of Patent: October 24, 2023
    Assignee: Amphenol Corporation
    Inventors: Marc B. Cartier, Jr., Mark W. Gailus, David Levine, Vysakh Sivarajan, John Robert Dunham, John Pitten
  • Patent number: D1002553
    Type: Grant
    Filed: November 3, 2021
    Date of Patent: October 24, 2023
    Assignee: Amphenol Corporation
    Inventors: Donald A. Girard, Jr., Barbara Calderon, Marc B. Cartier, Jr., David Levine, David Manter
  • Patent number: D1067191
    Type: Grant
    Filed: December 14, 2021
    Date of Patent: March 18, 2025
    Assignee: Amphenol Corporation
    Inventors: Marc B. Cartier, Jr., Mark W. Gailus, David Levine, Vysakh Sivarajan, John Robert Dunham, John Pitten
  • Patent number: D1068685
    Type: Grant
    Filed: December 14, 2021
    Date of Patent: April 1, 2025
    Assignee: Amphenol Corporation
    Inventors: Marc B. Cartier, Jr., Mark W. Gailus, David Levine, Vysakh Sivarajan, John Robert Dunham, John Pitten
  • Patent number: D1100851
    Type: Grant
    Filed: January 16, 2025
    Date of Patent: November 4, 2025
    Assignee: Amphenol Corporation
    Inventors: Marc B. Cartier, Jr., Mark W. Gailus, David Levine, Vysakh Sivarajan, John Robert Dunham, John Pitten
  • Patent number: D1100852
    Type: Grant
    Filed: March 11, 2025
    Date of Patent: November 4, 2025
    Assignee: Amphenol Corporation
    Inventors: Marc B. Cartier, Jr., Mark W. Gailus, David Levine, Vysakh Sivarajan, John Robert Dunham, John Pitten