Abstract: Examples herein disclose an identification of a set of skew requirements corresponding to a set of data signals. Based on the set of skew requirements, the examples prioritize an order of transmission for the set of data signals. The example queue the set of data signals in accordance with the prioritized order.

Abstract: Examples herein disclose an identification of a set of skew requirements corresponding to a set of data signals. Based on the set of skew requirements, the examples prioritize an order of transmission for the set of data signals. The example queue the set of data signals in accordance with the prioritized order.

Abstract: Some examples comprise a memory device including a memory region accessible by a receiving processing unit and a plurality of sending processing units, the memory region including a set of memory buffers identified by a set of buffer identifiers; a first FIFO buffer for communicating a first buffer identifier from the receiving processing unit to any of the sending processing units, the first buffer identifier corresponding to a memory buffer available for use by the any one sending processing unit in sending data to the receiving processing unit; and a second FIFO buffer for communicating a second buffer identifier to the receiving processing unit from any of the sending processing units, the second buffer identifier corresponding to a memory buffer containing data being sent to the receiving unit.

Abstract: Some examples comprise a memory device including a memory region accessible by a receiving processing unit and a plurality of sending processing units, the memory region including a set of memory buffers identified by a set of buffer identifiers; a first FIFO buffer for communicating a first buffer identifier from the receiving processing unit to any of the sending processing units, the first buffer identifier corresponding to a memory buffer available for use by the any one sending processing unit in sending data to the receiving processing unit; and a second FIFO buffer for communicating a second buffer identifier to the receiving processing unit from any of the sending processing units, the second buffer identifier corresponding to a memory buffer containing data being sent to the receiving unit.

Abstract: Redundant, fault-tolerant management fabric for multipartition servers are disclosed. In an exemplary embodiment, a method comprises connecting a plurality of rack system components to a first network segment, the connection including at least two physical links sharing a single network address. The method also comprises monitoring communications paths in the first network segment. The method also comprises switching communications from the first network segment to a failover network segment if there is a failure in any of the communications paths in the first network segment.

Abstract: A logic module for restoring stability to an unstable bus. The logic module includes logic for detecting that a communications error has occurred on the bus. The logic module also includes logic for stabilizing a slave device operating in a read mode. The logic module further includes logic for stabilizing the slave device operating in a write mode. The stabilizing of the slave device operating in a write mode occurs after stabilizing the slave device operating in a read mode.

Abstract: A method for restoring stability to an unstable bus includes cycling a clock of the bus a number of times, transmitting a stop bit, cycling a clock line of the bus at least one time and transmitting a stop bit immediately after an acknowledgment bit has been received by a bus master.

Abstract: A system comprising a plurality of subsystems and a master power sequencer. Each of the plurality of subsystems is coupled to an associated power switch and an associated slave power sequencer. The master power sequencer is coupled to each of the slave power sequencers and each of the power switches. Upon a slave power sequencer identifying a fault with its associated subsystem, the master power sequencer determines whether to provide power to any other subsystem. Further, the master power sequencer is configured to send a signal to each of the power switches indicating whether to provide power to the subsystem associated with each of the power switches.

Abstract: A method for restoring stability to an unstable bus includes cycling a clock of the bus a number of times, transmitting a stop bit, cycling a clock line of the bus at least one time and transmitting a stop bit immediately after an acknowledgment bit has been received by a bus master.

Abstract: A system comprising a clock board comprising a clock generator, a first board comprising an indicator and coupled to said clock board. The clock generator generates a clock signal, and the first board is configured to receive said clock signal. The first board further comprises a clock synchronizing unit that synchronizes a reference signal with said clock signal and generates a blink cadence signal based on said reference signal. The blink cadence signal is configured to drive the indicator of said first board. A failure by said first board to receive said clock signal causes the clock synchronizing unit of said first board to maintain the reference signal and generate said blink cadence signal based on said reference signal.

Abstract: Apparatus and other embodiments associated with a distributed Joint Test Access Group (JTAG) test bus controller (TBC) architecture are described. One example method includes providing first on-board scan programming (OSP) data to a first circuit board configured with a first TBC and located in a computer. The example method also includes providing second OSP data to a second circuit board configured with a second test bus controller and located in the same computer. The example method also includes controlling OSP to be performed at least partially in parallel on the first circuit board and the second circuit board.

Abstract: Redundant, fault-tolerant management fabric for multipartition servers are disclosed. In an exemplary embodiment, a method comprises connecting a plurality of rack system components to a first network segment, the connection including at least two physical links sharing a single network address. The method also comprises monitoring communications paths in the first network segment. The method also comprises switching communications from the first network segment to a failover network segment if there is a failure in any of the communications paths in the first network segment.

Abstract: Example apparatus and methods virtualize a circuit disposed between an input/output (I/O) hub and an I/O device. The I/O hub is configured to communicate PCIe slot control and status signals with an I/O device via an interface. The example apparatus and methods selectively intercept and transform signals passing between the I/O hub and the I/O device. The example apparatus and methods may also provide intercepted signals to a sideband monitor.

Abstract: A system comprising a clock board comprising a clock generator, a first board comprising an indicator and coupled to said clock board. The clock generator generates a clock signal, and the first board is configured to receive said clock signal. The first board further comprises a clock synchronizing unit that synchronizes a reference signal with said clock signal and generates a blink cadence signal based on said reference signal. The blink cadence signal is configured to drive the indicator of said first board. A failure by said first board to receive said clock signal causes the clock synchronizing unit of said first board to maintain the reference signal and generate said blink cadence signal based on said reference signal.

Abstract: A system comprising a plurality of subsystems and a master power sequencer. Each of the plurality of subsystems is coupled to an associated power switch and an associated slave power sequencer. The master power sequencer is coupled to each of the slave power sequencers and each of the power switches. Upon a slave power sequencer identifying a fault with its associated subsystem, the master power sequencer determines whether to provide power to any other subsystem. Further, the master power sequencer is configured to send a signal to each of the power switches indicating whether to provide power to the subsystem associated with each of the power switches.

Abstract: Apparatus and other embodiments associated with a distributed Joint Test Access Group (JTAG) test bus controller (TBC) architecture are described. One example method includes providing first on-board scan programming (OSP) data to a first circuit board configured with a first TBC and located in a computer. The example method also includes providing second OSP data to a second circuit board configured with a second test bus controller and located in the same computer. The example method also includes controlling OSP to be performed at least partially in parallel on the first circuit board and the second circuit board.

Abstract: One embodiment of a non-volatile memory system comprises block-accessible non-volatile memory, random access memory arranged to be linearly addressable by a processor as part of the processor's memory address space, to be read from and written to by the processor, and logic interposed between the block-accessible non-volatile memory and the random access memory and arranged to write parts of the content of the random access memory in blocks to blocks of the non-volatile, block-accessible memory. The logic is arranged to monitor processor writes to the random access memory, and to write blocks of the random access memory that differ from a most recent copy in the non-volatile, block-accessible memory to the non-volatile, block-accessible memory.

Abstract: One embodiment of a non-volatile memory system comprises block-accessible non-volatile memory, random access memory arranged to be linearly addressable by a processor as part of the processor's memory address space, to be read from and written to by the processor, and logic interposed between the block-accessible non-volatile memory and the random access memory and arranged to write parts of the content of the random access memory in blocks to blocks of the non-volatile, block-accessible memory. The logic is arranged to monitor processor writes to the random access memory, and to write blocks of the random access memory that differ from a most recent copy in the non-volatile, block-accessible memory to the non-volatile, block-accessible memory.

Abstract: Systems, methodologies, media, and other embodiments associated with general purpose event register blocks are described. One example system embodiment can include a general purpose event (GPE) register logic that can be configurable to provide multiple system control interrupt (SCI) output signals and be configurable to map selected event signals to selected SCI output signals where the multiple SCI output signals can be routed to multiple partitioned computer systems.

Abstract: A system, such as a complex computer system, incorporates several programmable logic devices coupled to load their configuration code from associated EEPROMs; typically this load is automatic on powerup. The EEPROMs connect to one of several serial busses, typically JTAG busses, connecting the EEPROMs with a common configuration logic. A processor is configured to write programmable logic configuration code from its memory through the common configuration logic and over the serial busses into the EEPROMs. The processor is also capable of connecting to a network and fetching configuration code for writing to the EEPROMs.