Abstract: A computer system is disclosed that includes: a communications bus implemented in accordance with an Inter-IC bus specification; a bus controller coupled to the communications bus; a send machine coupled between a host processor and the bus controller; and a first-in first-out (FIFO) buffer coupled to the send machine and coupled between the host processor and the bus controller.

Abstract: A machine-readable identification register is provided on each cell of a cellular computer system. The identification register is read during system startup to identify a processor type, which may include an instruction set architecture (ISA), associated with the cell. The processor type information is used to ensure that a compatible boot image is provided to processors of the cell. In another embodiment, the system management subsystem has a version selection flag. When the version selection flag is in a first state, the compatible boot image provided to processors of the cell is a current boot image; with the selection flag in a second state the compatible boot image provided to processors of the cell is an older edition of the boot image.

Abstract: A method and apparatus is described for the in-system programming of EEPROMs with configuration code for programmable logic devices such as FPGAs. The method and apparatus is suitable for use in larger systems where not all of the EEPROMs are located on the same circuit board. Multiple board-specific serial busses are provided, where each serial bus connects to EEPROMs of a particular circuit boards and to a common configuration point having selection apparatus and a header for coupling to configuration apparatus. The method includes the steps of setting the selection apparatus to designate a particular bus, erasing at least one EEPROM coupled to the serial bus, and writing programmable logic device configuration code through the serial bus to the EEPROM. Further claims include accessing the bus prior to writing any EEPROM to verify compatibility of a code file with the selected circuit board.

Abstract: A system, such as a complex computer system, incorporates several programmable logic devices coupled to load their configuration code from associated EEPROMs; typically this load is automatic on powerup. The EEPROMs connect to one of several serial busses, typically JTAG busses, connecting the EEPROMs with a common configuration logic. A processor is configured to write programmable logic configuration code from its memory through the common configuration logic and over the serial busses into the EEPROMs. The processor is also capable of connecting to a network and fetching configuration code for writing to the EEPROMs.