Patents by Inventor David Mark
David Mark has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 12131006Abstract: Aspects of the present disclosure involve a system comprising a computer-readable storage medium storing at least one program and a method for navigating an avatar based on time zones. A global event is identified that begins at a particular time on a given date; a sequential list of time zones associated with a plurality of geographical locations is retrieved; and a current time at a first time zone of the sequential list of time zones is determined to have reached the particular time on the given date. In response, an avatar is generated for display on a map at a first of the plurality of geographical locations associated with the first time zone and is navigated to a second geographical location when a current time at a second time zone, associated with the second geographical location, reaches the particular time on the given date.Type: GrantFiled: June 13, 2023Date of Patent: October 29, 2024Assignee: SNAP INC.Inventors: Sumbul Alvi, David Mark, Kimberly A. Phifer, Graham Reid, Suraj Vindana Samaranayake, Alexandre Valdetaro Porto
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Publication number: 20230325052Abstract: Aspects of the present disclosure involve a system comprising a computer-readable storage medium storing at least one program and a method for navigating an avatar based on time zones. A global event is identified that begins at a particular time on a given date; a sequential list of time zones associated with a plurality of geographical locations is retrieved; and a current time at a first time zone of the sequential list of time zones is determined to have reached the particular time on the given date. In response, an avatar is generated for display on a map at a first of the plurality of geographical locations associated with the first time zone and is navigated to a second geographical location when a current time at a second time zone, associated with the second geographical location, reaches the particular time on the given date.Type: ApplicationFiled: June 13, 2023Publication date: October 12, 2023Inventors: Sumbul Alvi, David Mark, Kimberly A. Phifer, Graham Reid, Suraj Vindana Samaranayake, Alexandre Valdetaro Porto
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Patent number: 11714524Abstract: Aspects of the present disclosure involve a system comprising a computer-readable storage medium storing at least one program and a method for navigating an avatar based on time zones. A global event is identified that begins at a particular time on a given date; a sequential list of time zones associated with a plurality of geographical locations is retrieved; and a current time at a first time zone of the sequential list of time zones is determined to have reached the particular time on the given date. In response, an avatar is generated for display on a map at a first of the plurality of geographical locations associated with the first time zone and is navigated to a second geographical location when a current time at a second time zone, associated with the second geographical location, reaches the particular time on the given date.Type: GrantFiled: April 20, 2021Date of Patent: August 1, 2023Assignee: SNAP INC.Inventors: Sumbul Alvi, David Mark, Kimberly A. Phifer, Graham Reid, Suraj Vindana Samaranayake, Alexandre Valdetaro Porto
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Publication number: 20210240315Abstract: Aspects of the present disclosure involve a system comprising a computer-readable storage medium storing at least one program and a method for navigating an avatar based on time zones. A global event is identified that begins at a particular time on a given date; a sequential list of time zones associated with a plurality of geographical locations is retrieved; and a current time at a first time zone of the sequential list of time zones is determined to have reached the particular time on the given date. In response, an avatar is generated for display on a map at a first of the plurality of geographical locations associated with the first time zone and is navigated to a second geographical location when a current time at a second time zone, associated with the second geographical location, reaches the particular time on the given date.Type: ApplicationFiled: April 20, 2021Publication date: August 5, 2021Inventors: Sumbul ALVI, David MARK, Kimberly A. PHIFER, Graham REID, Suraj Vindana SAMARANAYAKE, Alexandre VALDETARO PORTO
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Patent number: 11010022Abstract: Aspects of the present disclosure involve a system comprising a computer-readable storage medium storing at least one program and a method for navigating an avatar based on time zones. A global event is identified that begins at a particular time on a given date; a sequential list of time zones associated with a plurality of geographical locations is retrieved; and a current time at a first time zone of the sequential list of time zones is determined to have reached the particular time on the given date. In response, an avatar is generated for display on a map at a first of the plurality of geographical locations associated with the first time zone and is navigated to a second geographical location when a current time at a second time zone, associated with the second geographical location, reaches the particular time on the given date.Type: GrantFiled: April 10, 2020Date of Patent: May 18, 2021Assignee: Snap Inc.Inventors: Sumbul Alvi, David Mark, Kimberly A. Phifer, Graham Reid, Suraj Vindana Samaranayake, Alexandre Valdetaro Porto
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Publication number: 20200249804Abstract: Aspects of the present disclosure involve a system comprising a computer-readable storage medium storing at least one program and a method for navigating an avatar based on time zones. A global event is identified that begins at a particular time on a given date; a sequential list of time zones associated with a plurality of geographical locations is retrieved; and a current time at a first time zone of the sequential list of time zones is determined to have reached the particular time on the given date. In response, an avatar is generated for display on a map at a first of the plurality of geographical locations associated with the first time zone and is navigated to a second geographical location when a current time at a second time zone, associated with the second geographical location, reaches the particular time on the given date.Type: ApplicationFiled: April 10, 2020Publication date: August 6, 2020Inventors: Sumbul Alvi, David Mark, Kimberly A. Phifer, Graham Reid, Suraj Vindana Samaranayake, Alexandre Valdetaro Porto
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Patent number: 10656797Abstract: Aspects of the present disclosure involve a system comprising a computer-readable storage medium storing at least one program and a method for navigating an avatar based on time zones. A global event is identified that begins at a particular time on a given date; a sequential list of time zones associated with a plurality of geographical locations is retrieved; and a current time at a first time zone of the sequential list of time zones is determined to have reached the particular time on the given date. In response, an avatar is generated for display on a map at a first of the plurality of geographical locations associated with the first time zone and is navigated to a second geographical location when a current time at a second time zone, associated with the second geographical location, reaches the particular time on the given date.Type: GrantFiled: February 6, 2019Date of Patent: May 19, 2020Assignee: Snap Inc.Inventors: Sumbul Alvi, David Mark, Kimberly A. Phifer, Graham Reid, Suraj Vindana Samaranayake, Alexandre Valdetaro Porto
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Patent number: 8000519Abstract: A method of evaluating an inline inspection recipe compares the capture rate of metal pattern defects in bounding boxes arising from failed electrical test vectors to the capture rate after the bounding box is shifted. A difference between the first and second capture rates indicates whether the inline inspection recipe is valid for capturing killer defects, or if the inline inspection recipe needs to be adjusted. In a particular example, the electrical test vectors are directed at a selected patterned metal layer of an FPGA (M6), and the metal pattern defect data for the selected patterned metal layer is mapped to the bounding box determined by the electrical test vector.Type: GrantFiled: April 4, 2007Date of Patent: August 16, 2011Assignee: Xilinx, Inc.Inventors: Yongjun Zheng, David Mark, Joe W. Zhao, Felino Encarnacion Pagaduan
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Patent number: 7453261Abstract: A method of monitoring the functionality of a wafer probe is disclosed. The method comprises applying a multi-site probe to a plurality of semiconductor dies; comparing the failure rate of a first probe site of the multi-site probe with the failure rate of a second probe site of the multi-site probe for a test of the plurality of semiconductor dies; and determining that a probe site of the multi-site probe is defective based upon comparing the failure rate of the first probe site of the multi-site probe with the failure rate of the second probe site of the multi-site probe. A system for monitoring the functionality of a wafer probe site is disclosed.Type: GrantFiled: October 27, 2006Date of Patent: November 18, 2008Assignee: Xilinx, Inc.Inventor: David Mark
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Publication number: 20080129819Abstract: An autostereoscopic display system includes a lenticular lens display screen that projects a plurality of views of a scene from its front surface. A plurality of video projectors are disposed to the rear of the display screen and focus on a convergence point of the display screen's rear surface. Imaging computers drive the video projectors, each having a memory storing a scene to be displayed on the display screen. Each computer renders the scene from a preselected viewpoint that may be different from the viewpoints of the other imaging computers.Type: ApplicationFiled: February 4, 2008Publication date: June 5, 2008Applicant: Mark Resources, LLCInventors: David Mark, Brett C. Weichers
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Patent number: 7363560Abstract: According to one aspect of the invention, a circuit for determining the location of a defect in an integrated circuit is described. The circuit comprises a conductor extending from a first node to a second node and a test signal driver coupled to the first node of the conductor. The test signal driver receives a test signal using a first clock signal, while a plurality of detector circuits coupled to the conductor between the first node and the second node to detect an output at the plurality of nodes using a second clock signal. According to other embodiments, circuits for determining the location of a defect in a programmable logic device are disclosed. Finally, various methods for determining the location of a defect in an integrated circuit are described.Type: GrantFiled: February 23, 2005Date of Patent: April 22, 2008Assignee: Xilinx, Inc.Inventors: David Mark, Yuezhen Fan
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Patent number: 7262623Abstract: A method and test configuration for performing a gross I/O functionality test at wafer sort is described. The method uses a current injector, such as a pullup or a pulldown on an I/O pad, to inject current at the I/O pad, and based on the resulting voltage, determines if the I/O characteristics of the IC meet the performance criteria set by a manufacturer. In some embodiments, the test configuration can comprise an output buffer, which can be a tristate buffer, and/or an input buffer for verifying the performance of those components. The method and test configuration allow such tests to be performed at wafer sort without a precision measurement unit and without direct access to the I/O pad to be tested.Type: GrantFiled: July 14, 2003Date of Patent: August 28, 2007Assignee: Xilinx, Inc.Inventors: David Mark, Yung-Cheng Chen, Randy J. Simmons
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Patent number: 7227364Abstract: The embodiments of the present invention enable a new metal diagnosis pattern based on a production test pattern to quickly identify open and short circuits of metal lines which cannot be probed, such as the long lines of a programmable logic device, and to further isolates the fault location for physical failure analysis. According to one aspect of the invention, a circuit locally drives a plurality of metal long line segments to determine whether a defect in a line is a short circuit, or further to identify the location of an open circuit.Type: GrantFiled: December 16, 2004Date of Patent: June 5, 2007Assignee: Xilinx, Inc.Inventors: Yuezhen Fan, David Mark, Eric J Thorne, Zhi-Min Ling
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Publication number: 20060292638Abstract: Sequence #115, a G protein-coupled receptor, has been identified as a target for identifying weight modulating compounds. Compounds that modulate sequence #115 may be useful for the treatment of obesity and cachexia. Cell-based and cell-free assays are described to identify compounds which bind to and/or activate or inhibit the activity of sequence #115.Type: ApplicationFiled: September 1, 2006Publication date: December 28, 2006Inventors: Robert Goodnow, David Mark, Mitchell Martin, James Rosinski
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Patent number: 7145344Abstract: Described are methods and circuits for identifying defective device layers and localizing defects. Production PLD tests extract statistically significant data relating failed interconnect resources to the associated conductive metal layer. Failure data thus collected is then analyzed periodically to identify layer-specific problems. Test circuits in accordance with some embodiments employ interconnect resources heavily weighted in favor of specific conductive layers to provide improved layer-specific failure data. Some such test circuits are designed to identify open defects, while others are designed to identify short defects.Type: GrantFiled: November 7, 2003Date of Patent: December 5, 2006Assignee: Xilinx, Inc.Inventors: David Mark, Yuezhen Fan, Zhi-Min Ling, Xiao-Yu Li
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Patent number: 7124338Abstract: Methods and systems for testing PLD interconnect lines, e.g., interconnect lines driven by a plurality of programmable buffers. Each programmable buffer has an associated memory element. The memory elements are configured to form a shift register, with one of the buffers and the interconnect line inserted between two of the memory elements. The signal path through the shift register is tested using a first test pattern. Partial reconfiguration is then used to change the insertion point of the interconnect line in the signal path by changing the configuration of the interconnect structure and using a second one of the buffers. A second test pattern is then used to test the second buffer. This sequence is repeated until each of the buffers has been tested. Because only small changes are required, the partial reconfiguration requires loading only small amounts of configuration data, significantly reducing test time compared to presently-known test methods.Type: GrantFiled: October 10, 2003Date of Patent: October 17, 2006Assignee: Xilinx, Inc.Inventors: David Mark, Randy J. Simmons, Huy-Quang Le, Kazi S. Afzal
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Patent number: 6889368Abstract: Method and apparatus for localizing faults within an integrated circuit is described. For example, a programmable logic device (PLD) is configured with a test pattern. A test stimulus is applied to the test pattern. State data responsive to the test pattern is obtained. The state data may be obtained from a readback datastream generated by the PLD. The expected state data may be generated by a second PLD that is known to contain no faults. The state data is compared with expected state data to produce difference information. The difference information is used, or more particularly is iteratively generated, to localize a fault or faults within a unit under test.Type: GrantFiled: October 25, 2002Date of Patent: May 3, 2005Assignee: Xilinx, Inc.Inventors: David Mark, Randy J. Simmons, Min Luo
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Publication number: 20050062678Abstract: An autostereoscopic display system includes a lenticular lens display screen that projects a plurality of views of a scene from its front surface. A plurality of video projectors are disposed to the rear of the display screen and focus on a convergence point of the display screen's rear surface. Imaging computers drive the video projectors, each having a memory storing a scene to be displayed on the display screen. Each computer renders the scene from a preselected viewpoint that may be different from the viewpoints of the other imaging computers.Type: ApplicationFiled: September 24, 2004Publication date: March 24, 2005Inventors: David Mark, Brett Weichers
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Patent number: 6803912Abstract: A real time three dimensional multiple display imaging system has a central processing node and a plurality of remote, virtual camera processors. Each of the virtual cameras has its own predetermined viewpoint and is capable of displaying a scene into a virtual world from that viewpoint. The virtual world and the objects displayed in it are controlled by the central processing node. Geometric and textural data concerning the objects are stored in advance by memories associated with each one of the virtual cameras, thereby reducing the amount of communication bandwidth necessary for real-time animation.Type: GrantFiled: August 2, 2001Date of Patent: October 12, 2004Assignee: Mark Resources, LLCInventors: David Mark, Brett C. Weichers
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Patent number: 6788095Abstract: A method and test configuration for performing a gross input leakage test at wafer sort is described. The method uses a pullup and pulldown on an I/O pad to inject current at the I/O pad, and, based on the resulting voltage, determines if the leakage current is excessive. The method allows an input leakage test to be performed at wafer sort without a precision measurement unit and without direct access to the I/O pad to be tested.Type: GrantFiled: January 31, 2003Date of Patent: September 7, 2004Assignee: Xilinx, Inc.Inventors: David Mark, Randy J. Simmons