Patents by Inventor David May

David May has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20080229059
    Abstract: Each possessor node in an array of nodes has a respective local node address, and each local node address comprises a plurality of components having an order of addressing significance from most to least significant. Each node comprises: mapping means configured to map each component of the local node address onto a respective routing direction, and a switch arranged to receive a message having a destination node address identifying a destination node. The switch comprises: means for comparing the local node address to the destination node address to identify a the most significant non-matching component; and means for routing the message to another node, on the condition that the local node address does not match the destination node address, in the direction mapped to the most significant non-matching component.
    Type: Application
    Filed: March 14, 2007
    Publication date: September 18, 2008
    Inventor: Michael David May
  • Publication number: 20080229083
    Abstract: The invention provides a processor comprising an execution unit and a thread scheduler configured to schedule a plurality of threads for execution by the execution unit in dependence on a respective status for each thread. The execution unit is configured to execute thread scheduling instructions which manage said statuses, the thread scheduling instructions including at least: a thread event enable instruction which sets a status to event-enabled to allow a thread to accept events, a wait instruction which sets the status to suspended pending at least one event upon which continued execution of the thread depends, and a thread event disable instruction which sets the status to event-disabled to stop the thread from accepting events. The continued execution comprises retrieval of a continuation point vector for the thread.
    Type: Application
    Filed: March 14, 2007
    Publication date: September 18, 2008
    Inventor: Michael David May
  • Publication number: 20080066420
    Abstract: A protective sheet and method for protecting an object is disclosed. The protective sheet or drop cloth is made from a blend comprising ethylene vinyl acetate (EVA) and polyethylene (PE), making it naturally liquid impervious and slip resistant. The protective sheet includes a top side having a raised surface design configured for retaining fluid, and a bottom side that is smoother than the top side for added slip resistance. The method comprises the steps of providing the protective sheet and positioning it over the object, wherein the top side faces away from the object, and the bottom side faces the object and the top side is available for a workman to walk on.
    Type: Application
    Filed: September 6, 2007
    Publication date: March 20, 2008
    Inventor: David May
  • Publication number: 20080034162
    Abstract: A cache system is provided which includes a cache memory and a cache refill mechanism which allocates one or more of a set of cache partitions in the cache memory to an item in dependence on the address of the item in main memory. This is achieved in one of the described embodiments by including with the address of an item a set of partition selector bits which allow a partition mask to be generated to identify into which cache partition the item may be loaded.
    Type: Application
    Filed: July 26, 2007
    Publication date: February 7, 2008
    Applicant: STMicroelectronics Limited
    Inventors: Andrew Sturges, David May
  • Publication number: 20070152011
    Abstract: The disclosed invention is directed to an improved storage and dispensing device, comprising a container having a plurality of dowels for storing a dispensable object and at least one opening within the container through which the object can be dispensed. The invention allows a plurality of dispensable objects to be accessed and used without removing the objects from their stored position.
    Type: Application
    Filed: November 13, 2006
    Publication date: July 5, 2007
    Inventor: David May
  • Publication number: 20070077119
    Abstract: One exemplary optically active material includes a mark that facilitates identification of a preferred application orientation of the material without significantly affecting the optical properties of the material. Another exemplary optically active material is wound into a roll including multiple, individual strips of pre-measured tape. Adjacent strips are separated by a separation line that can be, for example, a perforated separation line or a complete cut that fully separates the adjacent strips.
    Type: Application
    Filed: October 5, 2005
    Publication date: April 5, 2007
    Inventors: Paul Northey, David May, Stephen Dvorsky, Michael Turner
  • Publication number: 20060054700
    Abstract: A card reader (30) for reading magnetic stripe cards (42), comprises a housing having a card entry slot, a magnetic read head (40) located within the housing and guide means (36) arranged to guide inserted cards to the read head to be read. The guide means (36) is arranged to displace a card laterally with respect to the entrance slot during insertion and withdrawal of the card.
    Type: Application
    Filed: September 1, 2005
    Publication date: March 16, 2006
    Inventor: David May
  • Publication number: 20050211143
    Abstract: A system and associated method of processing solid waste via a waste gasification process resulting in usable by-products may be used to generate electricity. The method utilizes a rotary kiln heated to a temperature of at least 800° F., a reduction chamber, heated to a temperature of at least 1800° F. and a boiler downstream of the reduction chamber. Steam generated in the boiler powers a turbine which operates a generator for generating electricity. Dampers may be positioned to bypass the power generation system. Gases are monitored and transported from the reduction chamber to at least one air pollution control unit to remove contaminants before being vented into the atmosphere.
    Type: Application
    Filed: May 17, 2005
    Publication date: September 29, 2005
    Applicant: Recycling Solutions Technology, LLC
    Inventors: David May, David May, John Burke
  • Publication number: 20050150924
    Abstract: The present invention is directed to an improved gift wrap storage and dispensing device, comprising a container and a lid, which are rotatable with respect to one another. Wrapping paper is stored on dowels within the container and is dispensed through openings in the side wall of the container. The wrapping paper is cut using a cutting device positioned on the outside wall of the container. Similarly, the lid contains a dispensing housing for storing rolls of tape, ribbon, etc., which can be dispensed through openings in the side wall of the lid and cut using a cutting device.
    Type: Application
    Filed: April 26, 2004
    Publication date: July 14, 2005
    Inventors: David May, Kirstin May
  • Publication number: 20050132141
    Abstract: A cache system is provided which includes a cache memory and a cache refill mechanism which allocates one or more of a set of cache partitions in the cache memory to an item in dependence on the address of the item in main memory. This is achieved in one of the described embodiments by including with the address of an item a set of partition selector bits which allow a partition mask to be generated to identify into which cache partition the item may be loaded.
    Type: Application
    Filed: January 28, 2005
    Publication date: June 16, 2005
    Applicant: STMicroelectronics Limited (formerly SGS-Thomson Microelectronics Limited
    Inventors: Andrew Sturges, David May
  • Patent number: 6871266
    Abstract: A cache system is provided which includes a cache memory and a cache refill mechanism which allocates one or more of a set of cache partitions in the cache memory to an item in dependence on the address of the item in main memory. This is achieved in one of the described embodiments by including with the address of an item a set of partition selector bits which allow a partition mask to be generated to identify into which cache partition the item may be loaded.
    Type: Grant
    Filed: May 23, 2003
    Date of Patent: March 22, 2005
    Assignee: STMicroelectronics Limited
    Inventors: Andrew Craig Sturges, David May
  • Publication number: 20050051066
    Abstract: A system and associated method of processing solid waste via a waste gasification process results in usable by-products. The method utilizes a rotary kiln heated to a temperature of at least 800° F. and a reduction chamber, heated to a temperature of at least 1800° F. The solid waste is slowly rotated in the kiln for six to eight hours. The solid material is passed through screens to separate the ash from other items. Gases are monitored and transported to the reduction chamber to generate power. The gases are then transported to at least one air pollution control unit to remove contaminants before being vented into the atmosphere.
    Type: Application
    Filed: September 4, 2003
    Publication date: March 10, 2005
    Applicant: Recycling Solutions Technology, LLC
    Inventors: David May, David May, John Burke
  • Patent number: 6757759
    Abstract: A computer system is formed by two interconnected chips each having on chip a CPU connected to a module by an on chip and data path, for distributing event request packets, the paths of the two chips being connected through external ports so that addresses on each of the paths form part of a common address space addressable from either chip.
    Type: Grant
    Filed: April 28, 1999
    Date of Patent: June 29, 2004
    Assignee: STMicroelectronics Limited
    Inventors: Andrew Michael Jones, Michael David May
  • Patent number: 6697931
    Abstract: There is disclosed a computer system including a microprocessor on a single integrated circuit chip comprising an on-chip CPU and a communication bus providing a parallel communication path between the CPU and at least one of the module with logic circuitry. The integrated circuit device further comprises an external communication port connected to the bus, having an internal parallel format for connection to the bus. The external port further has an external signal having an external format less parallel than the internal format. Translation circuitry is provided to effect conversion between said internal and external formats. There is also disclosed a method of operating such a computer system.
    Type: Grant
    Filed: July 25, 2000
    Date of Patent: February 24, 2004
    Assignee: STMicroelectronics Limited
    Inventors: Andrew Michael Jones, Michael David May
  • Patent number: 6658514
    Abstract: A computer system comprises on-chip a CPU with at least one different module, both having circuitry to generate two types of address request packets, one being a control command packet to which a destination device must respond on receipt and the other type being an interrupt request with a priority indicator for a selective response by the destination device.
    Type: Grant
    Filed: April 28, 1999
    Date of Patent: December 2, 2003
    Assignee: STMicroelectronics Limited
    Inventors: Andrew Michael Jones, Michael David May
  • Publication number: 20030196041
    Abstract: A cache system is provided which includes a cache memory and a cache refill mechanism which allocates one or more of a set of cache partitions in the cache memory to an item in dependence on the address of the item in main memory. This is achieved in one of the described embodiments by including with the address of an item a set of partition selector bits which allow a partition mask to be generated to identify into which cache partition the item may be loaded.
    Type: Application
    Filed: May 23, 2003
    Publication date: October 16, 2003
    Applicant: STMicroelectronics Limited
    Inventors: Andrew Craig Sturges, David May
  • Patent number: 6629208
    Abstract: A method of operating a cache memory is described in a system in which a processor is capable of executing a plurality of processes, each process including a sequence of instructions. In the method a cache memory is divided into cache partitions, each cache partition having a plurality of addressable storage locations for holding items in the cache memory. A partition indicator is allocated to each process identifying which, if any, of said cache partitions is to be used for holding items for use in the execution of that process. When the processor requests an item from main memory during execution of said current process and that item is not held in the cache memory, the item is fetched from main memory and loaded into one of the plurality of addressable storage locations in the identified cache partition.
    Type: Grant
    Filed: August 8, 2001
    Date of Patent: September 30, 2003
    Assignee: SGS-Thomson Microelectronics Limited
    Inventors: Andrew Craig Sturges, David May
  • Patent number: 6594729
    Abstract: A cache system is provided which includes a cache memory and a cache refill mechanism which allocates one or more of a set of cache partitions in the cache memory to an item in dependence on the address of the item in main memory. This is achieved in one of the described embodiments by including with the address of an item a set of partition selector bits which allow a partition mask to be generated to identify into which cache partition the item may be loaded.
    Type: Grant
    Filed: May 17, 1999
    Date of Patent: July 15, 2003
    Assignee: STMicroelectronics Limited
    Inventors: Andrew Craig Sturges, David May
  • Patent number: 6564314
    Abstract: A computer system has compact instructions avoiding the need for redundant bit locations and needing simple decoding. Logic circuitry is arranged to respond to an instruction set comprising a plurality of selectable instructions of different bit lengths. Each instruction is based on a format of predetermined bit length and a predetermined sequence of instruction fields each of a respective predetermined bit length. Some instructions omit a selected one of the fields and include an identifier of less bit length than the omitted field to indicate which field is omitted. Thus this bit length of the instruction is compressed. The logic circuitry is operable to restore the omitted field on execution of the instruction.
    Type: Grant
    Filed: June 7, 1995
    Date of Patent: May 13, 2003
    Assignee: SGS-Thomson Microelectronics Limited
    Inventors: Michael David May, Andrew Craig Sturges, Nathan Mackenzie Sidwell
  • Patent number: 6549965
    Abstract: A computer system provides on chip at least one CPU connected to another module by an address and data path, the module generating interrupt request packets with a destination address, the CPU decoding the packet, identifying a priority for the interrupt request and selectively responding to the request.
    Type: Grant
    Filed: April 28, 1999
    Date of Patent: April 15, 2003
    Assignee: STMicroelectronics Limited
    Inventors: Andrew Michael Jones, Michael David May