Abstract: A microcomputer comprises an integrated circuit device with processor and memory and communication links arranged to provide non-shared connections to similar links of other microcomputers. The communication links include message synchronisation and permit creation of networks of microcomputers with rapid communication between concurrent processes on the same or different microcomputers.

Abstract: A cache system and method of operating are described in which a cache is connected between a processor and a main memory of a computer. The cache system includes a cache memory having a set of cache partitions. Each cache partition has a plurality of addressable storage locations for holding items fetched from said main memory for use by the processor. The cache system also includes a cache refill mechanism arranged to fetch an item from the main memory and to load said item into the cache memory at one of said addressable storage locations in a cache partion wich depends on the address of said item in the main memory. This is achieved by a cache partition access table holding in association with addresses of items to be cached respective multi-bit partition indications identifying one or more cache partition into which the item is to be loaded.

Abstract: A computer system includes on-chip a CPU with an addressable module and a memory interface, the module having packet generating circuitry for event request or control packets, the CPU being operable to generate event request packets, memory access packets or control packets having a common format with packets generated by said module.

Abstract: A system and method for communication between a CPU and on-chip modules in an integrated circuit and off-chip devices is disclosed. A path on the integrated circuit allows for packet traffic to flow between the CPU and modules. In some embodiments the path is a data bus. Various types of packets are used, but each include a destination indicator to indicate the required destination device connected to the path. Data transfer packets are used for memory access operations. Normal event packets form prioritized interrupts wherein the recipient CPU or module respond to the event packet depending on relative priorities associated with other packets sent to the recipient device. Special event packets form command control signals that must be acted on by the recipient device when the special event packet is received.

Abstract: A microcomputer comprises an integrated circuit device with processor and memory and communication links arranged to provide non-shared connections to similar links of other microcomputers. The communication links include message synchronisation and permit creation of networks of microcomputers with rapid communication between concurrent processes on the same or different microcomputers.

Abstract: A cache system and method of operating are described in which a cache is connected between a processor and a main memory of a computer. The cache system includes a cache memory having a set of cache partitions. Each cache partition has a plurality of addressable storage locations for holding items fetched from said main memory for use by the processor. The cache system also includes a cache refill mechanism arranged to fetch an item from the main memory and to load said item into the cache memory at one of said addressable storage locations in a cache partion wich depends on the address of said item in the main memory. This is achieved by a cache partition access table holding in association with addresses of items to be cached respective multi-bit partition indications identifying one or more cache partition into which the item is to be loaded.

Abstract: A computer system includes an address and data path interconnecting an on-chip CPU with a module and an external communication port, event request packets being generated by the CPU and the module and memory access packets being generated by the CPU, each packet having a destination address and being distributed in parallel format on-chip with a reduction to a more serial format for off-chip communication.

Abstract: There is disclosed a computer system including a microprocessor on an integrated circuit chip comprising an on-chip CPU and a debugging port connected to a communication bus on the integrated circuit and to an external debugging computer device. The external debugging device is operable to transmit control signals through the debugging port: a) to stop execution by the CPU of instructions obtained from a first on-chip memory; b) to provide from a second memory associated with the external debugging computer device a debugging routine to be executed by the CPU; and c) to restart operation of the CPU after the routine with execution of instructions from an address determined by the external debugging device. The on-chip CPU is operable with code in the first memory which is independent of the debugging routine. A method of operating such a computer system with an external debugging device is also disclosed.

Abstract: A method of operating a cache memory is described in a system in which a processor is capable of executing a plurality of processes, each process including a sequence of instructions. In the method a cache memory is divided into cache partitions, each cache partition having a plurality of addressable storage locations for holding items in the cache memory. A partition indicator is allocated to each process identifying which, if any, of said cache partitions is to be used for holding items for use in the execution of that process. When the processor requests an item from main memory during execution of said current process and that item is not held in the cache memory, the item is fetched from main memory and loaded into one of the plurality of addressable storage locations in the identified cache partition.

Abstract: There is disclosed a computer,system including a microprocessor on an integrated circuit chip comprising an on-chip CPU and a communication bus. The communication bus provides a parallel communication path between the CPU and the first memory local to the CPU. An external port of the integrated circuit is connected to said bus and to an external computer device having a second memory. The external computer device is operable to transmit control signals through the port: a) to suspend execution by the CPU of instructions obtained from the first memory; b) to provide from the second memory boot code to be executed by the CPU; and c) to restart operation of the CPU using said boot code. There is also disclosed a method of operating such a computer system.

Abstract: A method of operating a cache memory is described in a system in which a processor is capable of executing a plurality of processes, each process including a sequence of instructions. In the method a cache memory is divided into cache partitions, each cache partition having a plurality of addressable storage locations for holding items in the cache memory. A partition indicator is allocated to each process identifying which, if any, of said cache partitions is to be used for holding items for use in the execution of that process. When the processor requests an item from main memory during execution of said current process and that item is not held in the cache memory, the item is fetched from main memory and loaded into one of the plurality of addressable storage locations in the identified cache partition.

Abstract: A manually operated, two lever arm type garlic press is provided which a detachably associated cleaning plate that is stored at the front end of the one of the lever arms (preferably, the first lever arm). The cleaning plate is provided with projections on its inner surface which are adopted to engage with apertures in the floor plate of the press chamber so as to clean debris from the apertures after usage of the garlic press. During storage, the projections extend forwardly from the associated lever arm. The cleaning plate is provided with opposing side clips and with top and bottom stabilizing legs that coact together and cooperate with side portions of the associated lever arm adjacent to the front end to hold the cleaning plate relative to that lever arm. Preferably, the top stabilizing leg also functions as a lock to retain the lever arms in a closed configuration during garlic press storage.

Abstract: The present invention is a device for storing and selectively sharpening a knife. The present invention includes a scabbard with opposing first and second ends. An opening is defined in the first end and a passage defined in the scabbard for receiving a knife blade. The device further includes a sharpening device and an engagement device, where the engagement device is in operable communication with the scabbard for selectively moving the sharpening device relative to the scabbard.

Abstract: A manually operated, two lever arm type garlic press is provided which a detachably associated cleaning plate that is stored at the front end of the one of the lever arms (preferably, the first lever arm). The cleaning plate is provided with projections on its inner surface which are adopted to engage with apertures in the floor plate of the press chamber so as to clean debris from the apertures after usage of the garlic press. During storage, the projections extend forwardly from the associated lever arm. The cleaning plate is provided with opposing side clips and with top and bottom stabilizing legs that coact together and cooperate with side portions of the associated lever arm adjacent to the front end to hold the cleaning plate relative to that lever arm. Preferably, the top stabilizing leg also functions as a lock to retain the lever arms in a closed configuration during garlic press storage.

Abstract: A hand held coring device for removing the core from a piece of fruit such as an apple, pear, or the like is disclosed. The device is constructed of a tube having a wall, a central bore, first and second ends, and at least two slots defined within the wall of the tube. The slots preferably extend from the first end of the tube to an area proximate to the second end. Additionally, the second end has a cutting edge for penetrating and cutting the fruit. The present corer has a plunger which is slidably positioned within the central bore of the tube and is linked, via at least two tab connectors, to an outer ring slidably positioned about a portion of the exterior of the tube. A movable guard to protect the cutting edge at the second end, where the guard includes the outer ring slidably positioned about a portion of the exterior of the tube is also featured.

Abstract: A computer system has instructions which have a reduction in the number of address bits relative to the number of data items that may be held during instruction execution. The instruction set comprises selectable instructions, a plurality of the instructions each including one set of bit locations identifying an operation to be carried out by execution of the instruction and a second set of bit locations to identify an address of a data storage location for use in execution of the instruction. The computer system further includes a plurality of addressable data storage locations for holding simultaneously a plurality of data values during execution of a sequence of instructions, with at least one of the data storage locations comprising a multi-value store requiring a single address in an instruction and arranged to hold a plurality of data values simultaneously on a first-in, first-out basis.

Abstract: A microcomputer comprises an integrated circuit device with processor and memory and communication links arranged to provide non-shared connections to similar links of other microcomputers. The communication links include message synchronisation and permit creation of networks of microcomputers with rapid communication between concurrent processes on the same or different microcomputers.