Abstract: In one particular implementation, a circuit includes: a flip flop; and an AND gate, where the circuit is configured to generate edge-triggered set and reset input signals. In another implementation, a method includes: providing, by a digital locked loop (DLL), a plurality of phase outputs; determining, by respective logic circuits, respective pulses to be selected for an output clock corresponding to each of the plurality phase outputs; shifting respective selection windows of the pulses such that each of the selection windows fully overlap the corresponding respective determined pulses; and selecting the pulses.

Abstract: Apparatus, method and code for fabrication of the apparatus, the apparatus comprising a cache providing a plurality of cache lines, each cache line storing a block of data; cache access control circuitry, responsive to an access request, to determine whether a hit condition is present in the cache; and cache configuration control circuitry to set, in response to a merging trigger event, merge indication state identifying multiple cache lines to be treated as a merged cache line to store multiple blocks of data, wherein when the merge indication state indicates that the given cache line is part of the merged cache line, the cache access control circuitry is responsive to detecting the hit condition to allow access to any of the data blocks stored in the multiple cache lines forming the merged cache line.

Abstract: Apparatus, method and code for fabrication of the apparatus, the apparatus comprising a cache providing a plurality of cache lines, each cache line storing a block of data; cache access control circuitry, responsive to an access request, to determine whether a hit condition is present in the cache; and cache configuration control circuitry to set, in response to a merging trigger event, merge indication state identifying multiple cache lines to be treated as a merged cache line to store multiple blocks of data, wherein when the merge indication state indicates that the given cache line is part of the merged cache line, the cache access control circuitry is responsive to detecting the hit condition to allow access to any of the data blocks stored in the multiple cache lines forming the merged cache line.

Abstract: In one particular implementation, a circuit includes: a flip flop; and an AND gate, where the circuit is configured to generate edge-triggered set and reset input signals. In another implementation, a method includes: providing, by a digital locked loop (DLL), a plurality of phase outputs; determining, by respective logic circuits, respective pulses to be selected for an output clock corresponding to each of the plurality phase outputs; shifting respective selection windows of the pulses such that each of the selection windows fully overlap the corresponding respective determined pulses; and selecting the pulses.

Abstract: Apparatuses and methods of data processing are disclosed for processing circuitry having a pipeline of multiple stages. Value prediction storage circuitry holds value predictions, each associated with an instruction identifier. The value prediction storage circuitry performs look-ups and provides the processing circuitry with data value predictions. The processing circuitry speculatively issues a subsequent instruction into the pipeline by provisionally assuming that execution of a primary instruction will result in the generated data value prediction. Allocation of entries into the value prediction storage circuitry is based on a dynamic allocation policy, whereby likelihood of allocation into the value prediction storage circuitry of an data value prediction increases for an executed instruction when the executed instruction is associated with at least one empty processing stage in the pipeline.

Abstract: An apparatus has processing circuitry for executing instructions and fetch circuitry for fetching the instructions for execution. When a branch instruction is encountered by the fetch circuitry, it determines subsequent instructions to be fetched in dependence on an initial branch direction prediction for the branch instruction made by branch prediction circuitry. Value prediction circuitry is used to maintain a predicted result value for one or more instructions, and dispatch circuitry maintains a record of pending instructions that have been fetched by the fetch circuitry and are awaiting execution by the processing circuitry, and selects pending instructions from the record for dispatch to the processing circuitry.

Abstract: A digital processor, method, and a non-transitory computer readable storage medium are described, and include a load pipeline operative to access a data content and convert the data content into a load result. The digital processor also includes a value prediction check circuit that is operative to access a speculative content, determine a predicted value from the speculative content, and determine a masked value by masking the data content with a data mask. The masked value is compared to the predicted value, and an action associated with the load result is commanded based upon the comparing of the masked value and the predicted value.

Abstract: A digital processor, method, and a non-transitory computer readable storage medium are described, and include a load pipeline operative to access a data content and convert the data content into a load result. The digital processor also includes a value prediction check circuit that is operative to access a speculative content, determine a predicted value from the speculative content, and determine a masked value by masking the data content with a data mask. The masked value is compared to the predicted value, and an action associated with the load result is commanded based upon the comparing of the masked value and the predicted value.

Abstract: An apparatus has processing circuitry for executing instructions and fetch circuitry for fetching the instructions for execution. When a branch instruction is encountered by the fetch circuitry, it determines subsequent instructions to be fetched in dependence on an initial branch direction prediction for the branch instruction made by branch prediction circuitry. Value prediction circuitry is used to maintain a predicted result value for one or more instructions, and dispatch circuitry maintains a record of pending instructions that have been fetched by the fetch circuitry and are awaiting execution by the processing circuitry, and selects pending instructions from the record for dispatch to the processing circuitry.

Abstract: An apparatus and method are provided for using predicted result values. The apparatus has a processing unit that comprises processing circuitry for executing a sequence of instructions, and value prediction circuitry for identifying a predicted result value for at least one instruction. A result producing structure is provided that is responsive to a request issued from the processing unit when the processing circuitry is executing a first instruction, to produce a result value for the first instruction and return that result value to the processing unit. While waiting for the result value from the result producing structure, the processing circuitry can be arranged to speculatively execute at least one dependent instruction using a predicted result value for the first instruction as obtained from the value prediction circuitry.

Abstract: An apparatus and method are provided for using predicted result values. The apparatus has processing circuitry for executing a sequence of instructions, and value prediction storage that comprises a plurality of entries, where each entry is used to identify a predicted result value for an instruction allocated to that entry. Dispatch circuitry maintains a record of pending instructions awaiting execution by the processing circuitry, and selects pending instructions from the record for dispatch to the processing circuitry for execution. The dispatch circuitry is arranged to enable at least one pending instruction to be speculatively executed by the processing circuitry using as a source operand a predicted result value provided by the value prediction storage. Allocation circuitry is arranged to apply a default allocation policy to identify a first instruction to be allocated an entry in the value prediction storage.

Abstract: An electronic device (20) has a clock path (24) for propagating a clock signal and a clock propagating element (26) on the clock path. An analogue element (30) coupled to the clock path (24) varies, in dependence on an analogue level of a first signal (32), a switching delay for the clock propagating element (26) to trigger a transition of the clock signal. The first signal is a digitally sampled signal. This provides a mechanism for providing a fast reduction in clock frequency even if the first signal is a metastable signal, which is useful for avoiding errors causes by voltage drops.

Abstract: An apparatus and method are provided for using predicted result values. The apparatus has a processing unit that comprises processing circuitry for executing a sequence of instructions, and value prediction circuitry for identifying a predicted result value for at least one instruction. A result producing structure is provided that is responsive to a request issued from the processing unit when the processing circuitry is executing a first instruction, to produce a result value for the first instruction and return that result value to the processing unit. While waiting for the result value from the result producing structure, the processing circuitry can be arranged to speculatively execute at least one dependent instruction using a predicted result value for the first instruction as obtained from the value prediction circuitry.

Abstract: An apparatus and method are provided for using predicted result values. The apparatus has processing circuitry for executing a sequence of instructions, and value prediction storage that comprises a plurality of entries, where each entry is used to identify a predicted result value for an instruction allocated to that entry. Dispatch circuitry maintains a record of pending instructions awaiting execution by the processing circuitry, and selects pending instructions from the record for dispatch to the processing circuitry for execution. The dispatch circuitry is arranged to enable at least one pending instruction to be speculatively executed by the processing circuitry using as a source operand a predicted result value provided by the value prediction storage. Allocation circuitry is arranged to apply a default allocation policy to identify a first instruction to be allocated an entry in the value prediction storage.

Abstract: A device comprises a coupling configured to couple signals to and from a communications path including at least a part of a human or animal body; a data transmitter coupled to the coupling and configured to transmit, from time to time, a data signal of at least a predetermined temporal duration via the communications path; and a data receiver coupled to the coupling and configured to detect the presence of a signal on the communications path at sets of one or more successive detection instances disposed between successive transmissions of the data signal by the data transmitter, the data receiver being configured so that the successive detection instances of a set are temporally separated by no more than the predetermined temporal duration; the device being configured to initiate a processing operation in response to a detection by the data receiver of the presence of a signal on the communications path.

Abstract: A transition detection circuit and method of operation of such a circuit are provided, the transition detection circuit having pulse generation circuitry to receive an input signal and to generate a pulse signal in response to a transition in the input signal, and pulse detection circuitry to assert an error signal on detection of the pulse signal generated by the pulse generation circuitry. The pulse generation circuitry has pulse control circuitry to control a property of the pulse signal dependent on a timing window indication signal. In particular, when the pulse signal is generated at least partly while the timing window indication signal is set, the pulse control circuitry controls the property of the pulse signal such that generated pulse signal is detected by the pulse detection circuitry.

Abstract: A storage bitcell comprising a first inverter cross-coupled with a second inverter, both the first and second inverter being in a path between a first potential and a second potential; wherein a first isolator is connected in the path between the first inverter and the first potential. The storage bitcell has particular application as Static Random-Access Memory (SRAM) circuitry.

Abstract: A method, system and surface covering for enabling wireless detection of damage to a structure is disclosed. At least one array having a plurality of nodes are coupled to a surface covering, such as at least one of a wall, ceiling and floor covering for a least a portion of the structure. An electronic reader is operable to wirelessly interrogate the array and read return signals from nodes in the array. The return signals contain data representing an ID for corresponding responsive nodes in the array, and the returned IDs are extracted and compared to a plurality of IDs stored in a data store for nodes in any given array. A mismatch between the returned and stored IDs for the nodes in the array indicates a structural defect in a respective portion of the structure overlaid by the floor/wall covering.

Abstract: A method, system and surface covering for enabling wireless detection of damage to a structure is disclosed. At least one array having a plurality of nodes are coupled to a surface covering, such as at least one of a wall, ceiling and floor covering for a least a portion of the structure. An electronic reader is operable to wirelessly interrogate the array and read return signals from nodes in the array. The return signals contain data representing an ID for corresponding responsive nodes in the array, and the returned IDs are extracted and compared to a plurality of IDs stored in a data store for nodes in any given array. A mismatch between the returned and stored IDs for the nodes in the array indicates a structural defect in a respective portion of the structure overlaid by the floor/wall covering.

Abstract: A storage bitcell comprising a first inverter cross-coupled with a second inverter, both the first and second inverter being in a path between a first potential and a second potential; wherein a first isolator is connected in the path between the first inverter and the first potential. The storage bitcell has particular application as Static Random-Access Memory (SRAM) circuitry.