Patents by Inventor David Naura

David Naura has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20070146174
    Abstract: A method divides a number N1 by a number which can be written in the form 2n/k, n and k being whole numbers, and obtains a result N2. The result N2 is calculated by adding terms N1*Ki/2n-i for i ranging from 0 to N, the terms Ki being the constituent bits K0, K1, K2, . . . KN-1 of the number k expressed in binary. The method can be applied particularly to the production of a calibration circuit for calibrating a clock signal in a UHF transponder.
    Type: Application
    Filed: December 19, 2006
    Publication date: June 28, 2007
    Applicant: STMicroelectronics SA
    Inventors: Christophe Moreaux, Ahmed Kari, David Naura, Pierre Rizzo
  • Patent number: 7237157
    Abstract: A procedure is provided for identifying an operating mode of a device, such as an EEPROM memory that communicates according to a communication protocol, such as “I2C” (Inter Integrated Circuit). The signal is an “ACK” or “ACKNOWLEDGE” signal. At least one operating mode of a device is identified by a time lag from the time the signal (ACK) is transmitted relative to the time foreseen by the protocol for the signal. This approach can be used to verify that the test mode commands (read or write) have been taken into account correctly.
    Type: Grant
    Filed: May 13, 2004
    Date of Patent: June 26, 2007
    Assignee: STMicroelectronics SA
    Inventors: David Naura, Bertrand Bertrand, Mohamad Chehadi
  • Publication number: 20070063879
    Abstract: A method for generating a variable number includes generating a clock signal, demodulating a received signal of data transmission, supplying a binary signal having variable frequency pulses, and sampling the clock signal by the binary signal to generate bits of a variable number. The method can be applied to RFID tags.
    Type: Application
    Filed: September 7, 2006
    Publication date: March 22, 2007
    Applicant: STMICROELECTRONICS SA
    Inventors: Christophe Moreaux, Ahmed Kari, David Naura, Pierre Rizzo
  • Publication number: 20070058430
    Abstract: A method protects against a global data erasure an integrated circuit comprising an electrically programmable data memory and a control unit to execute commands for reading or writing in the memory. The method comprises the steps of providing, in the integrated circuit, electrically programmable reference memory cells, at putting the integrated circuit into service, storing, in the reference memory cells, bits of determined value forming an authorized combination of bits and, during the operation of the integrated circuit following its putting into service, reading and evaluating the reference memory cells and blocking the integrated circuit if the reference memory cells contain a forbidden combination of bits different from the authorized combination.
    Type: Application
    Filed: August 31, 2006
    Publication date: March 15, 2007
    Applicant: STMicroelectronics SA
    Inventors: David Naura, Christophe Moreaux, Ahmed Kari, Pierre Rizzo
  • Publication number: 20070053233
    Abstract: A method checks the state of a set of memory cells of a memory comprising memory cells arranged in a memory array, means for selecting a memory cell, and a sense amplifier for supplying a state of the selected memory cell depending on whether the selected memory cell is conductive or non-conductive. The method includes features wherein all the memory cells of a set grouping together several memory cells are selected, and then simultaneously coupled to the sense amplifier, and the sense amplifier supplies a global state of all the selected memory cells to which it is coupled, if the latter are simultaneously non-conductive. Application is provided to the checking of a command for block-erasing a memory.
    Type: Application
    Filed: August 29, 2006
    Publication date: March 8, 2007
    Applicant: STMicroelectronics S.A.
    Inventors: David Naura, Christophe Moreaux, Ahmed Kari, Pierre Rizzo
  • Publication number: 20060115003
    Abstract: A method is provided for decoding an encoded binary data signal and generating a clock signal that is synchronous with the encoded data signal. There is generated, from the encoded data signal, an edge detection signal comprising four pulses per binary state of the encoded data signal. The encoded data signal is sampled every four pulses of the edge detection signal so as to obtain a binary signal of decoded data, and from the edge detection signal there is generated a binary clock signal that is synchronous with the encoded data signal and changes logic state every two pulses of the edge detection signal.
    Type: Application
    Filed: November 4, 2005
    Publication date: June 1, 2006
    Applicant: STMICROELECTRONICS SA
    Inventors: Ahmed Kari, David Naura
  • Patent number: 7012837
    Abstract: A method is provided for erasing or programming at least one memory cell of a non-volatile memory. According to the method, a state fixation pulse is applied to a floating gate transistor of the memory cell. The state fixation pulse also includes, successively, a portion at a reference voltage, and a state fixation portion at a voltage with sufficient amplitude for the transfer of electrons between the drain and the gate of the floating gate transistor. Additionally, an external adjustment signal is applied to the memory to adjust the state fixation portion to a predetermined duration, and the state fixation portion is adjusted to the predetermined duration in real time as a function of the state of the adjustment signal. Also provided is a non-volatile memory.
    Type: Grant
    Filed: July 31, 2004
    Date of Patent: March 14, 2006
    Assignee: STMicroelectronics, S.A.
    Inventors: David Naura, Bertrand Bertrand, Mohamad Chehadi
  • Publication number: 20050207230
    Abstract: A method is provided for erasing or programming at least one memory cell of a non-volatile memory. According to the method, a state fixation pulse is applied to a floating gate transistor of the memory cell. The state fixation pulse also includes, successively, a portion at a reference voltage, and a state fixation portion at a voltage with sufficient amplitude for the transfer of electrons between the drain and the gate of the floating gate transistor. Additionally, an external adjustment signal is applied to the memory to adjust the state fixation portion to a predetermined duration, and the state fixation portion is adjusted to the predetermined duration in real time as a function of the state of the adjustment signal. Also provided is a non-volatile memory.
    Type: Application
    Filed: July 31, 2004
    Publication date: September 22, 2005
    Applicant: STMICROELECTRONICS SA
    Inventors: David Naura, Bertrand Bertrand, Mohamad Chehadi
  • Publication number: 20050015533
    Abstract: A procedure is provided for identifying an operating mode of a device, such as an EEPROM memory that communicates according to a communication protocol, such as “I2C” (Inter Integrated Circuit). The signal is an “ACK” or “ACKNOWLEDGE” signal. At least one operating mode of a device is identified by a time lag from the time the signal (ACK) is transmitted relative to the time foreseen by the protocol for the signal. This approach can be used to verify that the test mode commands (read or write) have been taken into account correctly.
    Type: Application
    Filed: May 13, 2004
    Publication date: January 20, 2005
    Applicant: STMICROELECTRONICS SA
    Inventors: David Naura, Bertrand Bertrand, Mohamad Chehadi
  • Publication number: 20040217793
    Abstract: A comparator with two thresholds includes a two-threshold latch in which one input and one output respectively form an input and an output of the comparator. The latch has a first node between a first power supply terminal and the output of the latch. The comparator also includes a first negative feedback loop acting on the first node for setting the first threshold of the comparator as a function of a first power supply potential. The first threshold is also a function of a first reference potential that is stable.
    Type: Application
    Filed: March 30, 2004
    Publication date: November 4, 2004
    Applicant: STMicroelectronics SA
    Inventors: Bertrand Bertrand, Mohamad Chehadi, David Naura
  • Patent number: 6714450
    Abstract: An electrically programmable and erasable memory includes memory cells connected to word lines and to bit lines arranged in columns. Bit lines selection transistors are driven by bit lines selection signals. Column selection latches each includes a locking element for a column selection signal and a circuit for delivering a gate control signal which depends on the output of the locking element. Each column selection latch delivers, in addition to a gate control signal, a bit lines selection signal. This signal depends on the output of the locking element at least during programming and reading phases of the memory cells.
    Type: Grant
    Filed: March 18, 2002
    Date of Patent: March 30, 2004
    Assignee: STMicroelectronics SA
    Inventors: Bertrand Bertrand, Mohamad Chehadi, David Naura
  • Patent number: 6621737
    Abstract: A circuit produces a voltage for the erasure or programming of a memory cell. The circuit includes a capacitor, and a discharge circuit connected to a first terminal of the capacitor. The discharge circuit includes a first transistor, a drain of which is connected to the first terminal of the capacitor. The first transistor activates the discharge circuit when a discharge signal is received by a gate of the first transistor. The discharge circuit includes a slow discharge arm and a fast discharge arm parallel-connected to the source of the first transistor. The discharge circuit produces a low discharge current or a high discharge current for discharging the capacitor as a function of an operating mode selection signal.
    Type: Grant
    Filed: March 11, 2002
    Date of Patent: September 16, 2003
    Assignee: STMicroelectronics SA
    Inventors: David Naura, Bertrand Bertrand, Mohamad Chehadi
  • Patent number: 6538931
    Abstract: In a memory integrated circuit comprising an internal circuit for the generation of a programming high voltage and comprising a first pad designed to receive a main logic supply voltage below five volts, a second specific supply pad is designed to supply the high voltage generation circuit. This enables the by application of a specific logic supply voltage with a voltage level greater than that of the main logic supply voltage in test mode or in application mode.
    Type: Grant
    Filed: June 15, 2000
    Date of Patent: March 25, 2003
    Assignee: STMicroelectronics S.A.
    Inventors: Mohamad Chehadi, David Naura
  • Patent number: 6504791
    Abstract: A method of writing in page mode in an electrically erasable and programmable non-volatile memory includes an initialization phase of writing an information element for the selection of the page in a storage latch associated with a column of the non-volatile memory array, and the writing in a temporary memory of each of the data bits to be written in the page. A write phase includes the selection of rows of the non-volatile memory array according to the contents of the temporary memory. A page mode write circuit includes one latch per column of the non-volatile memory array to contain a page selection information element, and a control logic circuit to give the row selection signals as a function of the contents of the temporary memory in a phase for writing the column of the non-volatile memory array.
    Type: Grant
    Filed: September 12, 2000
    Date of Patent: January 7, 2003
    Assignee: STMicroelectronics S.A.
    Inventors: David Naura, Sebastien Zink, Bertrand Bertrand
  • Publication number: 20020163832
    Abstract: An electrically programmable and erasable memory includes memory cells connected to word lines and to bit lines arranged in columns. Bit lines selection transistors are driven by bit lines selection signals. Column selection latches each includes a locking element for a column selection signal and a circuit for delivering a gate control signal which depends on the output of the locking element. Each column selection latch delivers, in addition to a gate control signal, a bit lines selection signal. This signal depends on the output of the locking element at least during programming and reading phases of the memory cells.
    Type: Application
    Filed: March 18, 2002
    Publication date: November 7, 2002
    Applicant: STMicroelectronics S.A.
    Inventors: Bertrand Bertrand, Mohamad Chehadi, David Naura
  • Publication number: 20020126534
    Abstract: A circuit produces a voltage for the erasure or programming of a memory cell. The circuit includes a capacitor, and a discharge circuit connected to a first terminal of the capacitor. The discharge circuit includes a first transistor, a drain of which is connected to the first terminal of the capacitor. The first transistor activates the discharge circuit when a discharge signal is received by a gate of the first transistor. The discharge circuit includes a slow discharge arm and a fast discharge arm parallel-connected to the source of the first transistor. The discharge circuit produces a low discharge current or a high discharge current for discharging the capacitor as a function of an operating mode selection signal.
    Type: Application
    Filed: March 11, 2002
    Publication date: September 12, 2002
    Applicant: STMicroelectronics S.A.
    Inventors: David Naura, Bertrand Bertrand, Mohamad Chehadi
  • Patent number: 6385096
    Abstract: A column register of an integrated circuit memory, notably in EEPROM technology, is utilized in a method of writing a data word of 2p bits in the memory, where p is a non-zero whole number. The method includes the following steps: 1) erasing all the cells of the word; 2) loading 2q data in 2q high-voltage latches (HV1, HV3, HV5, HV7), and loading 2p-2q other data in the 2p-2q low-voltage latches (LV0, LV2, LV4, LV6); and 3) programming 2q cells of the memory (M0, M2, M4, M6) as a function of the data memorized in the 2q high-voltage latches; as well as repeating 2p-q−1 times the following steps: 4) loading, in the 2q high-voltage latches, of 2q other data that were loaded in the 2q low-voltage latches at step 2); and 5) programming 2q other cells of the memory (M1, M3, M5, M7) as a function of the data memorized in the 2q high-voltage latches.
    Type: Grant
    Filed: September 13, 2001
    Date of Patent: May 7, 2002
    Assignee: STMicroelectronics S.A.
    Inventors: Bertrand Bertrand, David Naura, Sébastien Zink
  • Patent number: 6359822
    Abstract: An integrated circuit serial access type memory, notably in EEPROM technology, includes a data input (DI) and a data output (DO), a defined memory plane (MM) organized in memory words, as well as a set (LAT) of column registers, one such register being associated with at least one memory word of the memory. The memory includes a writing circuit and/or a reading circuit. The writing circuit operates, during an operation for writing a binary word in a given memory word (M0-M7), for loading the binary data of the binary word received in series at the data input (DI) directly into respective storage and switching latches (HV0-HV7) of the column register (R1) associated with the memory word (M0-M7). The reading circuit operates, during an operation for reading a binary word in a memory word, for reading successively the binary data stored in the memory cells of the memory word and for delivering directly, in serial form, each binary data read to the data output (DO) of the memory.
    Type: Grant
    Filed: September 29, 2000
    Date of Patent: March 19, 2002
    Assignee: STMicroelectronics S.A.
    Inventors: Sébastien Zink, Bertrand Bertrand, David Naura
  • Publication number: 20020031015
    Abstract: A column register of an integrated circuit memory, notably in EEPROM technology, is utilized in a method of writing a data word of 2P bits in the memory, where p is a non-zero whole number.
    Type: Application
    Filed: September 13, 2001
    Publication date: March 14, 2002
    Applicant: STMicroelectronics S.A.
    Inventors: Bertrand Bertrand, David Naura, Sebastien Zink
  • Patent number: 6324117
    Abstract: The invention proposes a method of selecting a determined access line of a serial access type integrated circuit memory, a determined access line being selectable among a determined group of access lines (AL0-AL7) of the same nature, for example a group of bit lines or a group of word lines, a line code on p bits being respectively associated to each access line of the group, which consists in pre-activating all the access lines of the group, then ofdeactivating progressively the other access lines as a function of the bits (Ai) of the line code of the access line to select received in series via the serial data input of the memory such that, in the end, only the access line to be selected remains activated.
    Type: Grant
    Filed: September 29, 2000
    Date of Patent: November 27, 2001
    Assignee: STMicroelectronics S.A.
    Inventors: Sébastien Zink, Bertrand Bertrand, David Naura