Patents by Inventor David Naura

David Naura has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6307792
    Abstract: A column register of an integrated circuit memory, notably in EEPROM technology, is utilized in a method of writing a data word of 2p bits in the memory, where p is a non-zero whole number. The method includes the following steps: 1) erasing all the cells of the word; 2) loading 2q data in 2q high-voltage latches (HV1, HV3, HV5, HV7), and loading 2p−2q other data in the 2p−2q low-voltage latches (LV0, LV2, LV4, LV6); and 3) programming 2q cells of the memory (M0, M2, M4, M6) as a function of the data memorized in the 2q high-voltage latches; as well as repeating 2p−q−1 times the following steps: 4) loading, in the 2q high-voltage latches, of 2q other data that were loaded in the 2q low-voltage latches at step 2); and 5) programming 2q other cells of the memory (M1, M3, M5, M7) as a function of the data memorized in the 2q high-voltage latches.
    Type: Grant
    Filed: September 29, 2000
    Date of Patent: October 23, 2001
    Assignee: STMicroelectronics S.A.
    Inventors: Bertrand Bertrand, David Naura, S├ębastien Zink
  • Patent number: 6275413
    Abstract: In a EEPROM memory architecture organized into word columns that includes n memory cells per word column, there is, for each word of the column, one diffusion line to connect sources of the memory cells to a ground connection transistor using a source line. A word read access includes simultaneously selecting the word accessed in a read mode in a first group of memory cells, and an additional word in the second group of memory cells. Each column has n bit lines ranked 0 to n−1, each connected to the same ranked cells in the first group of memory cells.
    Type: Grant
    Filed: September 7, 2000
    Date of Patent: August 14, 2001
    Assignee: STMicroelectronics S.A.
    Inventor: David Naura
  • Patent number: 6219277
    Abstract: A device and method for the reading of cells of an EEPROM is provided. The device includes at least one reference cell and one circuit for comparison between a current flowing into the reference cell and a current flowing in a cell selected in read mode. The reference cell is in a programmed state. The programming of the reference cell is done after the control reading and during the integrated circuit power-on reset phase, activated by the powering on of the integrated circuit.
    Type: Grant
    Filed: April 27, 1999
    Date of Patent: April 17, 2001
    Assignee: STMicroelectronics S.A.
    Inventors: Jean Devin, David Naura, Sebastien Zink
  • Patent number: 6212112
    Abstract: A method for testing decoding circuits in a memory including a matrix of storage cells includes writing the same first word in all the storage cells, and then writing second words in the matrix such that each row and each column has at least one stored second word. The second words are different from the first words. If several second words are written in the same row or in the same column, then the second words are different from one another. Reading all the words in the memory permits verification of the integrity of the decoding circuits, and reduces the testing time of the memory.
    Type: Grant
    Filed: December 2, 1999
    Date of Patent: April 3, 2001
    Assignee: STMicroelectronics S.A.
    Inventors: David Naura, Frederic Moncada
  • Patent number: 6157227
    Abstract: A neutralization device to reset or inhibit at least certain electronic functions of an integrated circuit depending on the level of the supply voltage Vdd comprises a conditional feedback means to deactivate it especially in standby mode and then eliminate its consumption, and to reactivate it for certain modes of operation of the integrated circuit.
    Type: Grant
    Filed: December 18, 1997
    Date of Patent: December 5, 2000
    Assignee: SGS-Thomson Microelectronics SA
    Inventors: Thierry Giovinazzi, David Naura
  • Patent number: 6127898
    Abstract: A ring oscillator using CMOS technology having three logic gates, including a threshold amplifier, where the transistors that set the voltage rise threshold and the voltage drop threshold in the amplifier are controlled by a bias control circuit so that the ratio of voltage rise threshold to the voltage supply diminishes and the ratio of the voltage drop threshold to the voltage supply increases, when the supply voltage falls.
    Type: Grant
    Filed: January 12, 1998
    Date of Patent: October 3, 2000
    Assignee: SGS-Thomson Microelectroncs S.A.
    Inventor: David Naura
  • Patent number: 6125022
    Abstract: The invention relates to a device to neutralize an electronic circuit when it is being powered or disconnected. It can be applied more particularly to electronic circuits powered by low voltages on the order of 1.8 volts. The device of the invention is not significantly affected by variations, due to manufacturing conditions, in the values of its components. The invention may be applied to the field of programmable electrical memories.
    Type: Grant
    Filed: November 17, 1998
    Date of Patent: September 26, 2000
    Assignee: SGS-Thomas Microelectronics S.A.
    Inventor: David Naura
  • Patent number: 6125063
    Abstract: In a memory integrated circuit comprising an internal circuit for the generation of a programming high voltage and comprising a first pad designed to receive a main logic supply voltage below five volts, a second specific supply pad is designed to supply the high voltage generation circuit. This enables the application of a specific logic supply voltage with a voltage level greater than that of the main logic supply voltage in test mode or in application mode.
    Type: Grant
    Filed: September 16, 1998
    Date of Patent: September 26, 2000
    Assignee: STMicroelectronics S.A.
    Inventors: Mohamad Chehadi, David Naura
  • Patent number: 6118709
    Abstract: A device for the resetting of a memory circuit in integrated circuit form includes means to recognize a particular sequence on one or more external signals applied to the integrated circuit, different from the sequences of operational functioning of the integrated circuit.
    Type: Grant
    Filed: July 23, 1998
    Date of Patent: September 12, 2000
    Assignee: STMicroelectronics S.A.
    Inventors: Sebastien Zink, David Naura
  • Patent number: 6040994
    Abstract: A method for writing in an electrically erasable and programmable non-volatile memory (EEPROM, Flash EEPROM) includes keeping a gate of a selection transistor at its maximum value for the erasure or programming of a memory cell, so long as the potential at a drain or source of the transistor is not zero or at a very low level. This increases the lifetime of the selection transistors.
    Type: Grant
    Filed: October 27, 1998
    Date of Patent: March 21, 2000
    Assignee: STMicroelectronics S.A.
    Inventor: David Naura
  • Patent number: 6034895
    Abstract: A method and apparatus for the programming and erasure of a memory cell made out of floating-gate transistors and to the circuit pertaining thereto is described. It can be applied especially to non-volatile electrically erasable and programmable memories, for example EEPROMs and flash EPROMs. A programming voltage or erasure voltage comprising a voltage shift equal in value to a reference voltage is produced, followed by a voltage ramp comprising a rising phase followed possibly by voltage plateau, this voltage ramp being shifted in voltage by the value of the reference voltage and being followed, in turn, by a voltage drop. The value of the voltage shift is fixed at an intermediate value that is lower than the value of a so-called tunnel voltage of the memory cell but greater than the supply voltage.
    Type: Grant
    Filed: November 24, 1998
    Date of Patent: March 7, 2000
    Assignee: SGS-Thomson Microelectronics S.A.
    Inventors: David Naura, Jean Devin
  • Patent number: 5999447
    Abstract: A non-volatile electrically erasable and programmable memory provides both a SDP (software data protection) function and an OTP (one-time protection) function. The memory comprises a memory array having a plurality of memory cells each for storing an information bit. The memory further comprises at least one supplementary cell for storing a first state bit pertaining to the write-accessible (or non-write accessible) state of all the memory cells of the memory array, and at least one other supplementary cell for storing a second state bit relating to the blank state (or non-blank state) of a group of memory cells designed to be programmed only once by the user. A common management circuit for the SDP and OTP cells is located outside the memory array.
    Type: Grant
    Filed: November 25, 1998
    Date of Patent: December 7, 1999
    Assignee: STMicroelectronics S.A.
    Inventors: David Naura, Sebastien Zink
  • Patent number: 5995416
    Abstract: A method for the generation of voltage for the programming or erasure of a non-volatile memory cell is disclosed. Also disclosed is a circuit and a computer readable medium which implement the method. During an operation of programming or erasure in the memory, the slope P of the write voltage ramp is adapted to the number of memory cells to be programmed or erased simultaneously during this operation. This method is particularly useful in the field of non-volatile, electrically erasable and programmable memories.
    Type: Grant
    Filed: September 18, 1998
    Date of Patent: November 30, 1999
    Assignee: STMicroelectronics S.A.
    Inventors: David Naura, Sebastien Zink
  • Patent number: 5978268
    Abstract: A voltage circuit generates a programming or erasure voltage for programming or erasing a floating-gate memory. The voltage generator circuit includes a charge pump to provide a pumped voltage and a shaping circuit to provide the programming or erasing voltage from the pumped voltage. A switching circuit enables the pumped voltage to reach a sufficient level before the shaping circuit generates the programming or erasure voltage.
    Type: Grant
    Filed: October 27, 1998
    Date of Patent: November 2, 1999
    Assignee: STMicroelectronics S.A.
    Inventors: Sebastien Zink, David Naura
  • Patent number: 5946241
    Abstract: The disclosure relates to the field of memories in integrated circuit form. It can be applied more particularly to the field of EPROM or EEPROM type electrically programmable non-volatile memories. A memory array and read circuits are proposed in order to improve the time taken to read a data element. During a reading operation a read circuit is connected firstly to an erased cell and secondly to a programmed cell. The memory outputs a 1 for a read operation that access a first memory cell having an erased state and a second memory cell having a programmed cell, and further, the memory outputs a 0 for a read operation that access a first memory cell having a programmed state and a second memory cell having an erased state.
    Type: Grant
    Filed: August 7, 1997
    Date of Patent: August 31, 1999
    Assignee: SGS-Thomson Microelectronics S.A.
    Inventors: Sebastien Zink, David Naura
  • Patent number: 5886549
    Abstract: The invention relates to a device to neutralize an electronic circuit when it is being powered or disconnected. It can be applied more particularly to electronic circuits powered by low voltages on the order of 1.8 volts. The device of the invention is not significantly affected by variations, due to manufacturing conditions, in the values of its components. The invention may be applied to the field of programmable electrical memories.
    Type: Grant
    Filed: January 24, 1997
    Date of Patent: March 23, 1999
    Assignee: SGS-Thomson Microelectronics S.A.
    Inventor: David Naura
  • Patent number: 5883831
    Abstract: Disclosed is a serial access memory and a method of writing in said memory comprising at least one matrix of memory cells, a clock signal input terminal receiving a clock signal, a data input terminal receiving a defined number of data bits in series and a selection terminal receiving a selection signal, said method being initialized when the selection signal changes state from a first state to a second state. The writing in the matrix of memory cells occurs only if the selection signal goes from the second state to the first state during a window located just after the last of the data bits has been received.
    Type: Grant
    Filed: September 29, 1997
    Date of Patent: March 16, 1999
    Assignee: SGS-Thomson Microelectronics S.A.
    Inventors: Joaquim Ramon Lopez, David Naura
  • Patent number: 5883833
    Abstract: A method and apparatus for the programming and erasure of a memory cell made out of floating-gate transistors and to the circuit pertaining thereto is described. It can be applied especially to non-volatile electrically erasable and programmable memories, for example EEPROMs and flash EPROMs. A programming voltage or erasure voltage including a voltage shift equal in value to a reference voltage is produced, followed by a voltage ramp comprising a rising phase followed possibly by voltage plateau, this voltage ramp being shifted in voltage by the value of the reference voltage and being followed, in turn, by a voltage drop. The value of the voltage shift is fixed at an intermediate value that is lower than the value of a so-called tunnel voltage of the memory cell but greater than the supply voltage.
    Type: Grant
    Filed: August 27, 1996
    Date of Patent: March 16, 1999
    Inventors: David Naura, Jean Devin
  • Patent number: 5841270
    Abstract: A reference generator implemented in a MOS technology integrated circuit comprises a current mirror device having three pairs of transistors connected so as to obtain a stable voltage at the mid point of its second arm. This same generator also supplies a stable current.
    Type: Grant
    Filed: July 23, 1996
    Date of Patent: November 24, 1998
    Assignee: SGS-Thomson Microelectronics S.A.
    Inventors: Tien-Dung Do, David Naura