Abstract: A non-volatile memory cell and associated programming methods that allow for integration of non-volatile memory with other CMOS integrated circuitry utilizing standard CMOS processing. The non-volatile memory cell includes an antifuse element having a programming node and a capacitor element coupled to the antifuse element and configured to provide one or more voltage pulses to the programming node. The antifuse element is configured to have a changed resistivity after the programming node is subjected to the one or more voltage pulses, the change in resistivity representing a change in logic state. The antifuse element comprises a MOS transistor, its gate being coupled to one of the programming node and a control node, and its source and drain being coupled to the other one of the programming node and the control node. The MOS transistor is formed in a well and the source, drain and well are coupled to the same voltage level.

Abstract: A multiple time programmable non-volatile memory element and associated programming methods that allow for integration of non-volatile memory with other CMOS integrated circuitry utilizing standard CMOS processing. The multiple time programmable non-volatile memory element includes a capacitor, an access transistor that is electrically coupled to the capacitor at a connection node, and a plurality of one time programmable non-volatile memory cells. Each of the plurality of one time programmable non-volatile memory cells is electrically coupled to the connection node and includes a select transistor that is electrically coupled to an antifuse element. The antifuse element is configured to have changed resistivity in response to one or more voltage pulses received at the connection node, the change in resistivity representing a change in logic state.

Abstract: A non-volatile memory cell including an antifuse element having a programming node and a control node, a capacitor element, a precharge element, an access element, and a leakage element. The antifuse element is configured to have changed resistivity (representing a change in logic state) after the programming node is subjected to one or more voltage pulses. The capacitor element, coupled to the programming node, is configured to provide the one or more voltage pulses to the programming node. The precharge element, coupled to the programming node, is configured to increase the one or more voltage pulses provided to the programming to node. The access element, coupled to the control node, is configured to allow determination of the logic state of the antifuse element based on current flow through the access element. The leakage element is coupled to the control node and configured to modify the current flowing through the access element when the resistivity of the antifuse element has not been changed.

Abstract: Reduced-step CMOS processes for low-cost integrated circuits (ICs) and, more particularly, low-cost radio frequency identification (RFID) devices are disclosed. The CMOS processes disclosed provide sufficient device performance and reliability while reducing the number and complexity of required process steps, thereby reducing the cost for manufacturing ICs. By recognizing the particular needs for low-cost integrated circuits such as RFID devices (for example, reduced needs for performance, power and longevity) and by identifying a reduced set of CMOS process steps, an advantageous solution is achieved for producing low-cost integrated circuits and low-cost RFID devices.

Abstract: Reduced-step CMOS processes for low-cost integrated circuits (ICs) and, more particularly, low-cost radio frequency identification (RFID) devices are disclosed. The CMOS processes disclosed provide sufficient device performance and reliability while reducing the number and complexity of required process steps, thereby reducing the cost for manufacturing ICs. By recognizing the particular needs for low-cost integrated circuits such as RFID devices (for example, reduced needs for performance, power and longevity) and by identifying a reduced set of CMOS process steps, an advantageous solution is achieved for producing low-cost integrated circuits and low-cost RFID devices.

Abstract: Reduced-step CMOS processes for low-cost integrated circuits (ICs) and, more particularly, low-cost radio frequency identification (RFID) devices are disclosed. The CMOS processes disclosed provide sufficient device performance and reliability while reducing the number and complexity of required process steps, thereby reducing the cost for manufacturing ICs. By recognizing the particular needs for low-cost integrated circuits such as RFID devices (for example, reduced needs for performance, power and longevity) and by identifying a reduced set of CMOS process steps, an advantageous solution is achieved for producing low-cost integrated circuits and low-cost RFID devices.

Abstract: Reduced-step CMOS processes for low-cost integrated circuits (ICs) and, more particularly, low-cost radio frequency identification (RFID) devices are disclosed. The CMOS processes disclosed provide sufficient device performance and reliability while reducing the number and complexity of required process steps, thereby reducing the cost for manufacturing ICs. By recognizing the particular needs for low-cost integrated circuits such as RFID devices (for example, reduced needs for performance, power and longevity) and by identifying a reduced set of CMOS process steps, an advantageous solution is achieved for producing low-cost integrated circuits and low-cost RFID devices.

Abstract: A method and related embedded memories are disclosed for utilizing voltage gradients to guide dielectric breakdowns for non-volatile memory elements. Non-volatile memory cells and associated programming methods are also disclosed that allow for the integration of non-volatile memory with other intergrated curcuitry utilizing the standard CMOS processing used to manufacture the CMOS circuitry. The non-volatile memory cell includes an antifuse element having a programming node and a capacitor coupled to the programming node. The antifuse element includes a MOS transistor having its source and drain connected to one or more voltage levels, having a gate that provides the programming node, and having a dielectric layer that provides an antifuse function by breaking down when subjected to a plurality of voltage pulses applied through the capacitor element. To guide the breakdown locations within the dielectric, one or more voltage gradients are generated within the antifuse element to concentration current flow.

Abstract: A method and related embedded memories are disclosed for utilizing voltage gradients to guide dielectric breakdowns for non-volatile memory elements. Non-volatile memory cells and associated programming methods are also disclosed that allow for the integration of non-volatile memory with other integrated circuitry utilizing the standard CMOS processing used to manufacture the CMOS circuitry. The non-volatile memory cell includes an antifuse element having a programming node and a capacitor coupled to the programming node. The antifuse element includes a MOS transistor having its source and drain connected to one or more voltage levels, having a gate that provides the programming node, and having a dielectric layer that provides an antifuse function by breaking down when subjected to a plurality of voltage pulses applied through the capacitor element. To guide the breakdown locations within the dielectric, one or more voltage gradients are generated within the antifuse element to concentration current flow.

Abstract: A non-volatile memory cell and associated programming methods are disclosed that allow for the integration of non-volatile memory with other integrated circuitry utilizing the standard CMOS processing used to manufacture the CMOS circuitry. A capacitor element is used to provide programming voltages to the non-volatile memory cell. And in one embodiment, the non-volatile memory cell includes an antifuse element having a programming node and a capacitor coupled to the programming node, such that the antifuse element is configured to have reduced resistivity after the programming node is subjected to one or more voltage pulses with the change in resistivity representing a change in logic state, and such that the capacitor element is configured to provide the voltage pulses to the programming node.

Abstract: A non-volatile memory cell and associated programming methods are disclosed that allow for the integration of non-volatile memory with other integrated circuitry utilizing the standard CMOS processing used to manufacture the CMOS circuitry. A capacitor element is used to provide programming voltages to the non-volatile memory cell. And in one embodiment, the non-volatile memory cell includes an antifuse element having a programming node and a capacitor coupled to the programming node, such that the antifuse element is configured to have reduced resistivity after the programming node is subjected to one or more voltage pulses with the change in resistivity representing a change in logic state, and such that the capacitor element is configured to provide the voltage pulses to the programming node.

Abstract: A method and related embedded memories are disclosed for utilizing voltage gradients to guide dielectric breakdowns for non-volatile memory elements. Non-volatile memory cells and associated programming methods are also disclosed that allow for the integration of non-volatile memory with other integrated circuitry utilizing the standard CMOS processing used to manufacture the CMOS circuitry. The non-volatile memory cell includes an antifuse element having a programming node and a capacitor coupled to the programming node. The antifuse element includes a MOS transistor having its source and drain connected to one or more voltage levels, having a gate that provides the programming node, and having a dielectric layer that provides an antifuse function by breaking down when subjected to a plurality of voltage pulses applied through the capacitor element. To guide the breakdown locations within the dielectric, one or more voltage gradients are generated within the antifuse element to concentration current flow.

Abstract: A method and related embedded memories are disclosed for utilizing a plurality of voltage pulses to program non-volatile memory elements. Non-volatile memory cells and associated programming methods are also disclosed that allow for the integration of non-volatile memory with other integrated circuitry utilizing the standard CMOS processing used to manufacture the CMOS circuitry. The non-volatile memory cell includes an antifuse element having a programming node and a capacitor coupled to the programming node. To write the antifuse element, a plurality of voltage pulses are used to provide a rapid series of charge flows through the antifuse element. The antifuse element includes a MOS transistor having its source and drain connected to one or more voltage levels, having a gate that provides the programming node, and having a dielectric layer that provides an antifuse function by breaking down when subjected to a plurality of voltage pulses applied through the capacitor element.

Abstract: The present invention relates to a booster circuit including a first P-MOS transistor, the source of which is connected to a high voltage line; a second N-MOS transistor, the drain of which is connected to a first supply potential and the source of which is connected to the drain of the first transistor; a first capacitor connected between the gate of the first transistor and a terminal of reception of a first clock signal; a second capacitor connected between the gate of the second transistor and the reception terminal for the first clock signal; a third capacitor connected between the drain of the first transistor and a reception terminal for a second clock signal, complementary to the first clock signal; two precharge diodes the first capacitor from the high voltage line; and one precharge diode for the second capacitor.

Abstract: A voice announcement medication storage and dispensing device for patients. The storage and dispensing device comprises a medical storage portion and a closure portion with data storage means disposed within the closure portion. The device is activated by access to the storage container and can be programmed with medication information including medication dosage, schedule, medical warnings and patient information. The medication storage and dispensing device has a self-contained power source with a data processing and memory chip and electronic data interface with audio data output.

Abstract: A semiconductor memory device includes a ferroelectric memory having a non-volatile operation mode and a volatile operation mode; an input terminal to which an input signal indicating a voltage level of a power source voltage is input; a first signal generating circuit outputting a first control signal for regulating activation and inactivation of the non-volatile operation mode to the ferroelectric memory; and a second signal generating circuit outputting a second control signal for regulating the activation and inactivation of the non-volatile operation mode to the first signal generating circuit, based on the input signal. The non-volatile operation mode and the volatile operation mode are automatically switched with each other in accordance with changes in the voltage level of the power source voltage under a first operation condition, and only the volatile operation mode is activated under a second operation condition.

Abstract: A reference scheme for a Dynamic Shadow Random Access Memory which provides a reference voltage circuit used for determining the data state of a ferroelectric memory cell operating in either dynamic (DRAM) or nonvolatile (NVRAM) modes. The reference voltage circuit includes two ferroelectric capacitors with associated data state setting transistors such that in either DRAM or NVRAM operating mode, the two capacitors store opposite data states. The circuit also includes means for alternating the data state of each capacitor. In operation, the ferroelectric capacitors are discharged to associated bitlines producing voltages which are averaged to derive a half-state reference voltage level. The reference voltage is used to determine the state of an associated memory cell. Additionally, a ferroelectric memory circuit is provided which includes an array of reference voltage circuits configured and operated in a manner to reduce the fatigue and imprinting experienced by the reference capacitors.

Abstract: A semiconductor memory device includes: a plurality of bit lines disposed on a substrate; a plurality of word lines and a plurality of data lines disposed on the substrate in a direction crossing with the bit lines; a plurality of memory cells disposed in a matrix at portions corresponding to respective crossing points of the bit lines and the word lines, each of the plurality of memory cells having at least one switching transistor and at least one ferroelectric capacitor including a ferroelectric film as an insulating film to form a non-volatile ferroelectric memory storing information by a polarization direction of the ferroelectric film; a substrate voltage generating circuit which supplies a negative substrate voltage to the substrate; and a power-on reset circuit which output and applies a predetermined positive voltage to the word lines during a time period from a power-on until the substrate voltage is stabilized.

Abstract: The generator has an input stage (I) including a voltage divider for dividing the voltage between the power supply and the ground, having a node constituting the output of the input stage, and by a positive-feedback threshold loop, driven by another node of the voltage divider to make the voltage in the output node rise sharply when the voltage in the other node exceeds a threshold. A first Schmitt trigger (T1) is driven by the voltage rise front supplied by the input stage; and a former of output pulses (F) comprising a second Schmitt trigger (T2) is driven by circuit means adapted to directly apply to the second Schmitt trigger the voltage front arriving from the first Schmitt trigger and to restore the original voltage level with a preset delay.

Abstract: A power-on reset circuit for supplying a reset pulse when a supply voltage rises above a preset threshold includes a reference voltage generator connected between the supply voltage and ground for supplying a reference signal having a constant preset value when the supply voltage is greater than the preset threshold. A supply follower provides an input signal which follows the supply voltage with a preset reduction factor. A bistable comparator having a first input driven by the reference signal and a second input driven by the input signal switches from a first state to a second state when the input signal exceeds the reference signal.