Abstract: In one aspect, the present invention provides a wafer level optical assembly comprising a first wafer level optical element, the first wafer level optical element comprising a first alignment structure and a second wafer level optical element, the second wafer level optical element comprising a second alignment structure, wherein the first alignment structure contacts the second alignment structure.

Abstract: An optics block includes a substrate having first and second opposing surfaces, the substrate being a first material, a plurality of through holes extending in the substrate between the first and second opposing surface, a second material, different than the first material, filling a portion of the through holes and extending on a portion of the first surface of the substrate outside the through holes, and a first lens structure in the second material and corresponding to each of the through holes.

Abstract: A microelectronic assembly is disclosed that includes a semiconductor wafer with contacts, compliant bumps of dielectric material overlying the first surface of the semiconductor wafer, and a dielectric layer overlying the first surface of the semiconductor wafer and edges of the compliant bumps. The compliant bumps have planar top surfaces which are accessible through the dielectric layer. Conductive traces may be electrically connected with contacts and extend therefrom to overlie the planar top surfaces of the compliant bumps. Conductive elements may overlie the planar top surfaces in contact with the conductive traces.

Abstract: A microelectronic assembly includes first and second stacked microelectronic elements, each having spaced apart traces extending along a front face and beyond at least a first edge thereof. An insulating region can contact the edges of each microelectronic element and at least portions of the traces of each microelectronic element extending beyond the respective first edges. The insulating region can define first and second side surfaces adjacent the first and second edges of the microelectronic elements. A plurality of spaced apart openings can extend along a side surface of the microelectronic assembly. Electrical conductors connected with respective traces can have portions disposed in respective openings and extending along the respective openings. The electrical conductors may extend to pads or solder balls overlying a face of one of the microelectronic elements.

Abstract: A microelectronic assembly is disclosed that includes a semiconductor wafer with contacts, compliant bumps of dielectric material overlying the first surface of the semiconductor wafer, and a dielectric layer overlying the first surface of the semiconductor wafer and edges of the compliant bumps. The compliant bumps have planar top surfaces which are accessible through the dielectric layer. Conductive traces may be electrically connected with contacts and extend therefrom to overlie the planar top surfaces of the compliant bumps. Conductive elements may overlie the planar top surfaces in contact with the conductive traces.

Abstract: Optical imaging apparatus are provided having the desired focal properties, which can be manufactured and/or assembled at the wafer level.

Abstract: A microelectronic assembly includes first and second stacked microelectronic elements, each having spaced apart traces extending along a front face and beyond at least a first edge thereof. An insulating region can contact the edges of each microelectronic element and at least portions of the traces of each microelectronic element extending beyond the respective first edges. The insulating region can define first and second side surfaces adjacent the first and second edges of the microelectronic elements. A plurality of spaced apart openings can extend along a side surface of the microelectronic assembly. Electrical conductors connected with respective traces can have portions disposed in respective openings and extending along the respective openings. The electrical conductors may extend to pads or solder balls overlying a face of one of the microelectronic elements.

Abstract: A method is provided for forming a microelectronic package at a wafer level. Such method can include providing a semiconductor wafer having a surface with a pattern of electrical contacts thereon. An interposer component can be provided which has a compliant dielectric layer bonded to a conductive layer. A pattern of holes can be formed through the compliant dielectric layer and the conductive layer which corresponds to the pattern of electrical contacts. The compliant dielectric layer can be contacted with the semiconductor wafer surface so that the pattern of holes is in an aligned position with the pattern of contacts and the compliant dielectric layer and the semiconductor wafer surface then bonded in the aligned position to unite the semiconductor wafer and the interposer component to form a wafer level semiconductor package. The wafer level semiconductor package can be diced to form individual semiconductor chip packages.

Abstract: An optics block includes a substrate having first and second opposing surfaces, the substrate being a first material, a plurality of through holes extending in the substrate between the first and second opposing surface, a second material, different than the first material, filling a portion of the through holes and extending on a portion of the first surface of the substrate outside the through holes, and a first lens structure in the second material and corresponding to each of the through holes.

Abstract: Optical imaging apparatus are provided having the desired focal properties, which can be manufactured and/or assembled at the wafer level.

Abstract: Packaged microelectronic elements are provided. In an exemplary embodiment, a microelectronic element having a front face and a plurality of peripheral edges bounding the front face has a device region at the front face and a contact region with a plurality of exposed contacts adjacent to at least one of the peripheral edges. The packaged element may include a plurality of support walls overlying the front face of the microelectronic element such that a lid can be mounted to the support walls above the microelectronic element. For example, the lid may have an inner surface confronting the front face. In a particular embodiment, some of the contacts can be exposed beyond edges of the lid.

Abstract: A method is provided for fabricating a unit including a semiconductor element such as a sensor unit, e.g., for optical imaging. A semiconductor element has plurality of conductive features exposed at the front surface and semiconductive or conductive material exposed at least one of the front and rear surfaces. At least some of the conductive features are insulated from the exposed semiconductive or conductive material. By electrodeposition, an insulative layer is formed to overlie the at least one of exposed semiconductive material or conductive material. Subsequently, a plurality of conductive contacts and a plurality of conductive traces are formed overlying the electrodeposited insulative layer, the conductive traces connecting the conductive features to the conductive contacts. The unit can be incorporated in a camera module having an optical element in registration with an imaging area of the semiconductor element.

Abstract: A stacked microelectronic assembly is fabricated from a structure which includes a plurality of first microelectronic elements having front faces bonded to a carrier. Each first microelectronic element may have a first edge and a plurality of first traces extending along the front face towards the first edge. After exposing at least a portion of the first traces, a dielectric layer is formed over the plurality of first microelectronic elements. After thinning the dielectric layer, a plurality of second microelectronic elements are aligned and joined with the structure such that front faces of the second microelectronic elements are facing the rear faces of the plurality of first microelectronic elements. Processing is repeated to form the desirable number of layers of microelectronic elements. In one embodiment, the stacked layers of microelectronic elements may be notched at dicing lines to expose edges of traces, which may then be electrically connected to leads formed in the notches.

Abstract: A microelectronic assembly includes first and second stacked microelectronic elements, each having spaced apart traces extending along a front face and beyond at least a first edge thereof. An insulating region can contact the edges of each microelectronic element and at least portions of the traces of each microelectronic element extending beyond the respective first edges. The insulating region can define first and second side surfaces adjacent the first and second edges of the microelectronic elements. A plurality of spaced apart openings can extend along a side surface of the microelectronic assembly. Electrical conductors connected with respective traces can have portions disposed in respective openings and extending along the respective openings. The electrical conductors may extend to pads or solder balls overlying a face of one of the microelectronic elements.

Abstract: A chip-sized wafer level packaged device including a portion of a semiconductor wafer including a device, a packaging layer formed over the portion of the semiconductor wafer, the packaging layer including a material having thermal expansion characteristics similar to those of the semiconductor wafer and a ball grid array formed over a surface of the packaging layer and being electrically connected to the device.

Abstract: A stacked microelectronic unit is provided which can include a plurality of vertically stacked microelectronic elements (12, 12A) each having a front surface (117), contacts (22) exposed at the front surface, a rear surface (118) and edges (18, 20) extending between the front and rear surfaces. Traces (24) connected with the contacts may extend along the front surfaces towards edges of the microelectronic elements with the rear surface of at least one of the stacked microelectronic elements being adjacent to a top face (90) of the microelectronic unit. A plurality of conductors (66) may extend along edges of the microelectronic elements from the traces (24) to the top face (90). The conductors may be conductively connected with unit contacts (76) such that the unit contacts overlie the rear surface (118) of the at least one microelectronic element (12A) adjacent to the top face.

Abstract: The present invention provides wafer level optical elements that obviate a substrate wafer or a portion thereof disposed between optical structures or optical surfaces of the element.

Abstract: A method is provided for fabricating a unit including a semiconductor element such as a sensor unit, e.g., for optical imaging. A semiconductor element has plurality of conductive features exposed at the front surface and semiconductive or conductive material exposed at at least one of the front and rear surfaces. At least some of the conductive features are insulated from the exposed semiconductive or conductive material. By electrodeposition, an insulative layer is formed to overlie the at least one of exposed semiconductive material or conductive material. Subsequently, a plurality of conductive contacts and a plurality of conductive traces are formed overlying the electrodeposited insulative layer, the conductive traces connecting the conductive features to the conductive contacts on the rear surface. The unit can be incorporated in a camera module having an optical element in registration with an imaging area of the semiconductor element.

Abstract: A microelectronic assembly is disclosed that includes a semiconductor wafer with contacts, compliant bumps of dielectric material overlying the first surface of the semiconductor wafer, and a dielectric layer overlying the first surface of the semiconductor wafer and edges of the compliant bumps. The compliant bumps have planar top surfaces which are accessible through the dielectric layer. Conductive traces may be electrically connected with contacts and extend therefrom to overlie the planar top surfaces of the compliant bumps. Conductive elements may overlie the planar top surfaces in contact with the conductive traces.

Abstract: A chip-sized wafer level packaged device including a portion of a semiconductor wafer including a device, a packaging layer formed over the portion of the semiconductor wafer, the packaging layer including a material having thermal expansion characteristics similar to those of the semiconductor wafer and a ball grid array formed over a surface of the packaging layer and being electrically connected to the device.