Abstract: A method for constructing a solenoid inductor of an IC package with active/passive devices includes positioning an inner winding substantially around a magnetic core, positioning an outer winding substantially around the inner winding, and using a layered process to perform positioning the inner and outer windings. The layered process includes processing a first conducting layer as a bottom layer of the outer winding, above processing a first dielectric layer, above processing a second conducting layer as a bottom layer of the inner winding, above processing a second dielectric layer, above processing a magnetic core layer, above processing a third dielectric layer, above processing a third conducting layer as a top layer of the inner winding, above processing a fourth dielectric layer, above processing a fourth conducting layer as a top layer of the outer winding, above processing a fifth dielectric layer, and the inner and outer windings are electrically connected.

Abstract: This application describes electronic circuit packages and methods of manufacture. The package (100, 300) includes a primary integrated circuit die (101) with a smaller secondary integrated circuit die (102) attached to a first surface of the primary integrated circuit die in a first location. A first set of electrical connectors (103) extend from the first surface of the primary integrated circuit die outside the first location to a package connection layer (106) to provide electrical connection between the package connection layer and the primary integrated circuit die. An intermediate layer (108) of dielectric or insulating material extends between the primary integrated circuit die and the package connection layer so that the dielectric or insulating material surrounds the first set of electrical connectors and there is at least some dielectric or insulating material between the second integrated circuit die and the package connection layer.

Abstract: A packaged semiconductor die may include a package terminal array comprising a plurality of terminals, wherein a spacing between the plurality of terminals of the ball grid array is less than 0.5 mm. First and second high-voltage circuits of the die may output a differential signal to a first and second terminal that may exceed 15 volts, in which the first high-voltage circuit and the second high-voltage circuit are positioned symmetrically around an axis and in which the first terminal and the second terminal are located at an edge of the package terminal array. A low-voltage circuit may be coupled to a third terminal and positioned between the first high-voltage circuit and the second high-voltage circuit, wherein the low-voltage circuit comprises circuitry organized in columns aligned along an axis and having a width defined by a fraction of the terminal spacing pitch.

Abstract: A method for constructing a solenoid inductor includes positioning an inner winding substantially around a magnetic core, positioning an outer winding substantially around the inner winding, and using a layered process to perform said positioning the inner and outer windings. The layered process includes processing a first conducting layer as a bottom layer of the outer winding, above processing a first dielectric layer, above processing a second conducting layer as a bottom layer of the inner winding, above processing a second dielectric layer, above processing a magnetic core layer, above processing a third dielectric layer, above processing a third conducting layer as a top layer of the inner winding, above processing a fourth dielectric layer, above processing a fourth conducting layer as a top layer of the outer winding, above processing a fifth dielectric layer, and the inner and outer windings are electrically connected.

Abstract: A packaged semiconductor die may include a package terminal array comprising a plurality of terminals, wherein a spacing between the plurality of terminals of the ball grid array is less than 0.5 mm. First and second high-voltage circuits of the die may output a differential signal to a first and second terminal that may exceed 15 volts, in which the first high-voltage circuit and the second high-voltage circuit are positioned symmetrically around an axis and in which the first terminal and the second terminal are located at an edge of the package terminal array. A low-voltage circuit may be coupled to a third terminal and positioned between the first high-voltage circuit and the second high-voltage circuit, wherein the low-voltage circuit comprises circuitry organized in columns aligned along an axis and having a width defined by a fraction of the terminal spacing pitch.

Abstract: The disclosure relates to integrated circuits and methods of manufacture. A method involves forming a first set of one or more circuit layers on a semiconductor substrate, placing at least one prefabricated layer portion onto the first set of circuit layers to form a component, and forming a second set of one or more circuit layers over the first set of circuit layers and the at least prefabricated layer portion. The prefabricated layer portion may be a magnetic layer portion placed to form a magnetic component such as a magnetic core of an inductor or transformer. The method may also comprise forming the prefabricated layer portion.

Abstract: The Application describes a substrate design for a MEMS transducer package. The substrate is defined by a conductive layer which forms the upper and lower surfaces of the substrate. The substrate is also provided with a conductive portion which is electrically isolated from the rest of the conductive layer. The conductive portion is supported between a first plane defined by the upper surface of the substrate and a second plane defined by the lower surface of the substrate by an electrically insulating moulding substance.

Abstract: The application relates to a MEMS transducer package comprising: a package substrate the package substrate comprising a substrate channel, the substrate channel comprising first and second channel portions, wherein the first portion extends in a first direction between a first channel opening in a side surface of the substrate and a junction between the first and second channel portions, and wherein the second portion extends in a second direction between said junction and a second channel opening at, or underlying, a substrate opening provided in an upper surface of the package substrate.

Abstract: A method for constructing a solenoid inductor includes positioning an inner winding substantially around a magnetic core, positioning an outer winding substantially around the inner winding, and using a layered process to perform said positioning the inner and outer windings. The layered process includes processing a first conducting layer as a bottom layer of the outer winding, above processing a first dielectric layer, above processing a second conducting layer as a bottom layer of the inner winding, above processing a second dielectric layer, above processing a magnetic core layer, above processing a third dielectric layer, above processing a third conducting layer as a top layer of the inner winding, above processing a fourth dielectric layer, above processing a fourth conducting layer as a top layer of the outer winding, above processing a fifth dielectric layer, and the inner and outer windings are electrically connected.

Abstract: A semiconductor device may include an integrated circuit die and a thin metal layer applied and conformed to one or more surfaces of the integrated circuit die in order to shield active circuitry of the integrated circuit die from light.

Abstract: The Application describes a substrate design for a MEMS transducer package. The substrate is defined by a conductive layer which forms the upper and lower surfaces of the substrate. The substrate is also provided with a conductive portion which is electrically isolated from the rest of the conductive layer. The conductive portion is supported between a first plane defined by the upper surface of the substrate and a second plane defined by the lower surface of the substrate by an electrically insulating moulding substance.

Abstract: The application describes a moulded interposer member for a MEMS transducer package. The interposer member comprises a void region and at least one through hole or channel.

Abstract: The application relates to a MEMS transducer package comprising: a package substrate the package substrate comprising a substrate channel, the substrate channel comprising first and second channel portions, wherein the first portion extends in a first direction between a first channel opening in a side surface of the substrate and a junction between the first and second channel portions, and wherein the second portion extends in a second direction between said junction and a second channel opening at, or underlying, a substrate opening provided in an upper surface of the package substrate.

Abstract: A package for a MEMS device, the package comprising a MEMS transducer within a chamber of the package; and a package substrate, wherein an upper surface of the package substrate defines at least part of a surface of the chamber; wherein the package substrate comprises a plurality of metal layers, the package substrate further comprising at least a part of a filter circuit for filtering RF signals, wherein a first metal layer is provided in a first plane of the substrate and wherein a resistor of the filter circuit is provided in a plane below the first plane.

Abstract: The application describes a package for a MEMS transducer. The package has a package substrate having an acoustic port formed in the package substrate. The acoustic port comprises a first acoustic port volume portion and a second acoustic port volume portion, the first acoustic port volume portion being separated from the second acoustic port volume potion by a discontinuity in a sidewall of the substrate. The cross sectional area of the first acoustic port volume portion is greater than the cross sectional area of the second acoustic port volume portion. A barrier may be attached to the upper surface of the package substrate so as to seal or cover the acoustic port.

Abstract: A MEMS transducer package comprising a substrate; a filter circuit for filtering RF signals, the filter circuit comprising a resistor and a capacitor; and an IPD chip; wherein at least a portion of the filter circuit is provided within the IPD chip.

Abstract: A package for a MEMS device, the package comprising a MEMS transducer within a chamber of the package; and a package substrate, wherein an upper surface of the package substrate defines at least part of a surface of the chamber; wherein the package substrate comprises a plurality of metal layers, the package substrate further comprising at least a part of a filter circuit for filtering RF signals, wherein a first metal layer is provided in a first plane of the substrate and wherein a resistor of the filter circuit is provided in a plane below the first plane.

Abstract: The application describes a package design for a MEMS transducer having an integrated circuit mounted within a chamber of the package. The integrated circuit may extend into a side wall recess of the package.

Abstract: The application describes a package for a MEMS transducer. The package has a package substrate having an acoustic port formed in the package substrate. The acoustic port comprises a first acoustic port volume portion and a second acoustic port volume portion, the first acoustic port volume portion being separated from the second acoustic port volume potion by a discontinuity in a sidewall of the substrate. The cross sectional area of the first acoustic port volume portion is greater than the cross sectional area of the second acoustic port volume portion. A barrier may be attached to the upper surface of the package substrate so as to seal or cover the acoustic port.

Abstract: A MEMS transducer package comprising a substrate; a filter circuit for filtering RF signals, the filter circuit comprising a resistor and a capacitor; and an IPD chip; wherein at least a portion of the filter circuit is provided within the IPD chip.