Patents by Inventor David Paul Jones
David Paul Jones has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20100251940Abstract: A one-piece pallet for securing and stacking drums thereon may include a tray having downwardly and inwardly tapering peripheral side walls, a top surface having a plurality of raised support surfaces, each shaped to engage a bottom of a container, a plurality of raised dividers, each of said dividers being positioned between adjacent support surfaces and being shaped to engage a side wall of a drum resting on said adjacent support surfaces. The side walls may have outer raised ribs terminating adjacent one of the support surfaces and shaped to engage a side wall of a drum resting on said adjacent one of said support surfaces. The dividers may include inner raised ribs having terminal portions opposite the terminal portions of the outer raised ribs such that a drum resting on any one of said support surfaces is constrained by the terminal portions of the inner and outer raised ribs from lateral movement relative to the tray.Type: ApplicationFiled: April 2, 2010Publication date: October 7, 2010Applicant: THE FABRI-FORM COMPANYInventors: David Paul Jones, Roy Lee Fehrman, JR.
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Publication number: 20100215826Abstract: The present invention discloses formulations for sheeted, baked fruit and vegetable crackers that have a light, crispy texture similar to a potato chip or cracker. Undehydrated ingredients are combined with dry ingredients and oil to make a dough, which is then sheeted and cut into pieces. The pieces are baked to produce vegetable and fruit snack crackers.Type: ApplicationFiled: February 26, 2009Publication date: August 26, 2010Applicant: FRITO-LAY TRADING COMPANY GMBHInventors: Gordon Douglas Campbell, David Paul Jones, Joanna Louise Peart, Andrew Paul Thomas
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Patent number: 7691708Abstract: A MOSgated trench device has a reduced on resistance by forming a less than about a 13 nm thick strained SiGe layer on the silicon surface of the trenches and forming a thin (30 nm or less) layer of epitaxially deposited silicon on the SiGe layer which epi layer is converted to a gate oxide layer. The conduction channel formed by the SiGe layer is permanently strained to increase its mobility particularly hole mobility.Type: GrantFiled: May 17, 2007Date of Patent: April 6, 2010Assignee: International Rectifier CorporationInventors: David Paul Jones, Robert P. Haase
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Patent number: 7682935Abstract: A process is described to enable the manufacture of a thinned (<50 ?m semiconductor die) which can employ the use of standard equipment for the manufacture of the wafer and the packaging of the die singulated from the wafer. A standard thickness wafer (350 ?m) first has junctions formed in its upper surface, but the surface is not yet metallized and patterned. A rigid front plate is connected to the upper surface by a removable adhesive and the wafer is back ground to its final thickness, for example, less than 50 ?m. A back metal and a thick conductive backing plate are then fixed to the back metal. The rigid front plate is then removed and the front surface of the wafer is metallized and patterned. Die singulated from the wafer carry the thick permanent conductive backing plate and may be conventionally packaged as prior art 350 ?m die. The wafer can initially be partially diced.Type: GrantFiled: June 8, 2006Date of Patent: March 23, 2010Assignee: International Rectifier CorporationInventors: Hugo R. G. Burke, David Paul Jones
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Publication number: 20090263952Abstract: A process for fabrication of a semiconductor device that includes forming a first trench in a semiconductor body, forming spaced spacers in the first trench, and forming a narrower second trench at the bottom of the first trench using the spacers as a mask.Type: ApplicationFiled: March 23, 2009Publication date: October 22, 2009Inventors: Vijay Viswanathan, Dev Alok Girdhar, Timothy Henson, David Paul Jones
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Publication number: 20090218684Abstract: A power semiconductor package that includes a power semiconductor device having a threshold voltage that does not vary when subjected to an autoclave test.Type: ApplicationFiled: January 26, 2009Publication date: September 3, 2009Inventors: Mark Pavier, Danish Khatri, Daniel Cutler, Andrew Neil Sawle, Susan Johns, Martin Carroll, David Paul Jones
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Publication number: 20090212435Abstract: A power semiconductor device that includes a stack of a thin metal layer and a thick metal layer over the active region thereof, and a method for the fabrication thereof.Type: ApplicationFiled: February 25, 2008Publication date: August 27, 2009Inventors: Robert Montgomery, Hugo Burke, Philip Parsonage, Susan Johns, David Paul Jones
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Patent number: 7517810Abstract: A process for etching a thick aluminum contact layer of a semiconductor wafer comprises the formation of a wet etch photoresist mask and the opening of a window in the mask, followed by a wet etch of a first portion of the thickness of the contact layer exposed by the window and the inherent under cutting of the contact layer under the mask window. A dry etch is next carried out, using the same window as a mask, to cut the remaining web of the contact layer under the window. An etch stop layer of Ti or TiN can be formed within the body of the contact layer to define the depth of the initial wet etch into the contact layer.Type: GrantFiled: May 26, 2006Date of Patent: April 14, 2009Assignee: International Rectifier CorporationInventors: David Paul Jones, Hugo R. G. Burke
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Patent number: 7465986Abstract: A power semiconductor device includes a plurality of trenches formed within a semiconductor body, each trench including one or more electrodes formed therein. In particular, according to embodiments of the invention, the plurality of trenches of a semiconductor device may include one or more gate electrodes, may include one or more gate electrodes or one or more source electrodes, or may include a combination of both gate and source electrodes formed therein. The trenches and electrodes may have varying depths within the semiconductor body.Type: GrantFiled: August 25, 2005Date of Patent: December 16, 2008Assignee: International Rectifier CorporationInventors: Dev Alok Girdhar, Ling Ma, Steven T. Peake, David Paul Jones
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Patent number: 7456470Abstract: A top drain MOSgated device has its drain on the top of semiconductor die and its source on the bottom of the die substrate. Parallel spaced trenches extend from the die top surface through a drift region, a channel region and terminate on the substrate region. The bottoms of each trench receive a silicide conductor to short the substrate source to channel regions. The silicide conductors are then insulated at their top surfaces and gate electrodes are placed in the same trenches as those receiving the channel/source short.Type: GrantFiled: September 29, 2005Date of Patent: November 25, 2008Assignee: International Rectifier CorporationInventor: David Paul Jones
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Publication number: 20080275328Abstract: A body function sensor (1, 2, 3) for detecting breathing or heart beat or the like has an RF source (5) driving a transmit antenna (20) to create a low frequency (LF) electromagnetic detection field at a location to be occupied by an animal body. A receive antenna (21) is arranged to drive an analyser means (23, 13, 15,) to produce a signal representing the difference between the transmitted and detected signals detect a change in the field caused by the breathing or heart beat of an animal body in the location. A control means (16) controls the frequency of the RF source (5) to ensure resonance, and also controls the analyser means (23, 13), a display monitor (17) and an alarm. A memory (18) records movements of the subject, breathing patterns, pulse rate and posture of the body.Type: ApplicationFiled: December 27, 2007Publication date: November 6, 2008Inventor: David Paul Jones
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Patent number: 7439580Abstract: A trench type top drain MOSgated device has a drain electrode on the die top and a source electrode on the die bottom surface. The device is turned on by a control voltage connected between a drain and a gate region. The device cell has a body short trench and a gate trench. Gate poly is disposed in the bottom of the gate trench and is disposed adjacent a thin gate oxide lining a channel region with minimum overlap of the drain drift region. The bottom of the body short trench contains a contact which shorts the body region to the channel region. The body short, top drain region and gate polysilicon are simultaneously silicided. The gate trench is widened at its top to improve Qgd characteristics. Both the body short trench and gate trench are simultaneously filled with gap fill material.Type: GrantFiled: September 1, 2005Date of Patent: October 21, 2008Assignee: International Rectifier CorporationInventors: Daniel M. Kinzer, David Paul Jones, Kyle Spring
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Patent number: 7423317Abstract: A power semiconductor device which includes gate liners extending along gate insulation liners and an insulation block spacing the two gate liners.Type: GrantFiled: July 24, 2006Date of Patent: September 9, 2008Assignee: International Rectifier CorporationInventors: Hugo R. G. Burke, David Paul Jones, Ling Ma, Robert Montgomery
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Patent number: 7238985Abstract: A MOSgated trench device has a reduced on resistance by forming a less than about a 13 nm thick strained SiGe layer on the silicon surface of the trenches and forming a thin (30 nm or less) layer of epitaxially deposited silicon on the SiGe layer which epi layer is converted to a gate oxide layer. The conduction channel formed by the SiGe layer is permanently strained to increase its mobility particularly hole mobility.Type: GrantFiled: August 4, 2004Date of Patent: July 3, 2007Assignee: International Rectifier CorporationInventors: David Paul Jones, Robert P. Haase
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Patent number: 7145452Abstract: Detection of the presence of an animal body, for instance a human, in a detection zone is achieved by generating a low power LF field (17) between antennae (12, 18), and by measuring the disturbance of this field by the body. An analyser (16) is used detect such disturbance by measuring changes in the phase of the received signal (19).Type: GrantFiled: January 16, 2003Date of Patent: December 5, 2006Assignee: Intelligent Sensors PLCInventor: David Paul Jones
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Patent number: 6887743Abstract: Methods of forming a gate dielectric layer, and a composite gate dielectric layer, for a thin film transistor, has been developed. A first embodiment of this invention describes the procedure used to create the composite gate dielectric layer. A first, thin silicon oxide gate dielectric layer is thermally grown on an underlying active semiconductor layer, such as polysilicon. A first anneal procedure, is performed at a temperature greater than the temperature used for the thermal growth of this layer, resulting in improved parametric integrity. A thicker, second silicon oxide gate dielectric layer is then thermally deposited, followed by an anneal procedure used to provide a composite gate dielectric layer comprised of a densified, thermally deposited second silicon oxide gate dielectric layer, on an underlying, thermally grown first silicon oxide gate dielectric layer.Type: GrantFiled: February 2, 2001Date of Patent: May 3, 2005Assignee: International Rectifier CorporationInventors: Richard Bullock, David Paul Jones
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Patent number: 6848114Abstract: A system for providing access to a plurality of data media contained in a data storage system is provided. The data storage system comprises a plurality of media storage devices for storing the plurality of data media, a data exchange device for exchanging data stored on the plurality of data media, and a media handling system for transferring the plurality of data media between the plurality of media storage devices and the data exchange device. The system comprises a bulk access apparatus configured to cover a plurality of openings in the data storage system. Each of the plurality of openings in the data storage system provide access to one of the media storage devices.Type: GrantFiled: August 23, 2001Date of Patent: January 25, 2005Assignee: Hewlett-Packard Development Company, L.P.Inventors: Robert Lee Mueller, Paul Clinton Coffin, David Paul Jones
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Patent number: 6733223Abstract: Systems and methods for providing a removable media handling system in a data storage system are provided. Briefly described, in one of many possible embodiments the data storage system comprises a plurality of housings, a media handling system, and a lift system. The plurality of housings are arranged in vertical stacks and each of the plurality of housings is configured to receive one or more media storage devices that are configured to receive a plurality of data media. The media handling system is configured to access the plurality of data media received by the media storage device. The lift assembly is configured to move the media handling system vertically between the plurality of housings. The media handling system and the lift assembly are configured such that the media handling system is removably attached to the lift assembly.Type: GrantFiled: August 23, 2001Date of Patent: May 11, 2004Assignee: Hewlett-Packard Development Company, L.P.Inventors: Robert Lee Mueller, Paul Clifton Coffin, David Paul Jones
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Patent number: 6559914Abstract: A liquid crystal display device is described in which the TFTs are located directly below the spaces between pixels. The black matrix comprises an array of opaque conductive elements with one such element being above each TFT. The black matrix is incorporated into the TFT structure. By using highly conductive material for the black matrix elements their thickness is held to a minimum, thereby minimizing their impact on planarity. Optionally, this highly conductive layer may be laminated with layers of a non-reflective conductor that makes good ohmic contact to silicon. In one embodiment, metal filled via holes are added that connect the TFTs to the transparent conductive pixel control elements by way of the black matrix layer. In another embodiment, the black matrix layer is connected to be in parallel with the gate electrode, thereby reducing the series resistance of the latter. A process for manufacturing the display is also described.Type: GrantFiled: July 5, 2001Date of Patent: May 6, 2003Assignee: International Rectifier Corp.Inventors: David Paul Jones, Richard Bullock
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Publication number: 20030049105Abstract: Systems and methods for providing a removable media handling system in a data storage system are provided. Briefly described, in one of many possible embodiments the data storage system comprises a plurality of housings, a media handling system, and a lift system. The plurality of housings are arranged in vertical stacks and each of the plurality of housings is configured to receive one or more media storage devices that are configured to receive a plurality of data media. The media handling system is configured to access the plurality of data media received by the media storage device. The lift assembly is configured to move the media handling system vertically between the plurality of housings. The media handling system and the lift assembly are configured such that the media handling system is removably attached to the lift assembly.Type: ApplicationFiled: August 23, 2001Publication date: March 13, 2003Inventors: Robert Lee Mueller, Paul Clinton Coffin, David Paul Jones