Abstract: A method for manufacturing semiconductor devices can include forming an anti-spacer pattern including anti-spacer trenches, formed between a first patterned photoresist layer and a patterned overcoat layer, and extending along a first direction, forming a first patterned hard mask layer having first contact trenches extending along the first direction using the anti-spacer pattern, where the first patterned hard mask layer is formed from a first hard mask layer of underlying layers, forming a second patterned photoresist layer, where the second patterned photoresist layer includes contact-edge features and second contact trenches overlapping with the first contact trenches of the first patterned hard mask layer, where the contact-edge features and the second contact trenches extend in a second direction that is non-parallel with the first direction; and self-aligned etching using the second patterned photoresist layer and the first patterned hard mask layer to form third contact trenches.

Abstract: This disclosure provides methods and systems of processing a semiconductor wafer. One method includes obtaining wafer characterization metrology information of a wafer, the wafer including a plurality of dies, and generating a plurality of predicted die shapes based on the wafer characterization metrology information being input into a computing model. Each of the plurality of predicated die shapes corresponds to one of the plurality of dies of the wafer. The method further includes processing the wafer to obtain the plurality of dies and processing the plurality of dies based on the plurality of predicated die shapes.

Abstract: A method of forming a patterned metal layer on a substrate includes identifying at least one distortion zone in a design pattern of metal structures causing a Z-direction displacement of the substrate, inserting metal fill shapes as a fill pattern into the design pattern to reduce the Z-direction displacement in the at least one distortion zone, and forming the metal structures and the metal fill shapes on the substrate as the patterned metal layer. The method may further include calculating bond strength of the substrate based on the design pattern and the fill pattern and adjusting surface area of the metal fill shapes to increase the bond strength. A bonded substrate structure may then be formed by directly bonding a dielectric material of the patterned metal layer of the substrate to an additional substrate.

Abstract: A process includes forming, over a dielectric layer, a hardmask stack including a first layer below a second layer below a third layer below a fourth layer. The first and third layers include a different hardmask material from the second and fourth layers. A trench pattern including sidewall spacer structures is formed over the hardmask stack. The fourth layer is etched in a first region. The fourth and third layers are etched in a second region. The fourth and third layers are etched in a third region. The fourth layer is etched in a fourth region. The second and first layers are etched in the second and third regions. The third layer is etched in the first and fourth regions. In the dielectric layer, trenches are formed in the first and fourth regions, and via openings, deeper than the trenches, are formed in the second and third regions.

Abstract: A method includes providing a carrier substrate having a die bonded thereto, where the die includes a first alignment mark on a first surface. The method includes positioning a target substrate with a second surface on a substrate stage, where the target substrate includes a second alignment mark on the second surface. The method includes positioning the carrier substrate with respect to a die handler, where the die handler includes a third alignment mark. The method includes coupling the die to the die handler, where the step of coupling includes aligning the first alignment mark with the third alignment mark. The method includes positioning the coupled die and the die handler over the target substrate, where the step of positioning includes aligning the second alignment mark with at least one of the first alignment mark and the third alignment mark. The method includes bonding the first surface with the second surface.

Abstract: Aspects of the present disclosure provide an apparatus that heats a semiconductor structure while holding the semiconductor structure. For example, the apparatus can include a semiconductor structure holding device that is configured to hold the semiconductor structure. The apparatus can also include a heating device that is configured to generate a certain pattern of heat. The heating device can be integrated with the semiconductor structure holding device such that when the semiconductor structure holding device is holding the semiconductor structure, the certain pattern of heat generated by the heating device can be applied to the semiconductor structure.

Abstract: A method for patterning a substrate, the method includes forming a first mask over the substrate, the first mask including first features and first spaces and exposing the substrate at a bottom of each first space; forming a second mask while retaining the first features, the second mask including second features and second spaces, the second features covering a portion of the substrate exposed by the first spaces; and either selectively depositing on or selectively removing material from the second features relative to the first features to change a width of each of the second features.

Abstract: Aspects of the present disclosure provide an apparatus that heats a semiconductor structure while holding the semiconductor structure. For example, the apparatus can include a semiconductor structure holding device that is configured to hold the semiconductor structure. The apparatus can also include a light projection device that is configured to generate a certain pattern of light. The light projection device can be integrated with the semiconductor structure holding device such that when the semiconductor structure holding device is holding the semiconductor structure, the certain pattern of light generated by the light projection device is projected onto the semiconductor structure holding device and a corresponding certain pattern of heat is generated and transferred through the semiconductor structure holding device and applied to the semiconductor structure, in order to correct the shape and size of the semiconductor structure.

Abstract: Aspects of the present disclosure provide a method for chemical mechanical polishing (CMP) iso-dense bias compensation using z-height. For example, the method can include forming a dielectric material on a substrate within a first region to form one or more first dielectric layers that are spaced from one another, and forming on a first one of the first dielectric layers a first height correction layer that has a first height that is determined based on a first pattern density of the first region. The method can also include depositing a conductive material on the substrate to fill one or more first trenches surrounded by the first dielectric layers and the first height correction layer and cover the first dielectric layers and the first height correction layer, and performing a planarization process to planarize the conductive material and the first height correction layer until uncovering the first dielectric layers.

Abstract: Aspects of the present disclosure provide a die-to-wafer (D2W) shape correction and bonding method. For example, the method can include providing a wafer and a chiplet, forming a shape control layer on at least one of the wafer and the chiplet, activating the shape control layer according to a bow measurement of the at least one of the wafer and the chiplet to modify an internal stress of the shape control layer, and bonding the wafer and the chiplet, at least one of which has the shape control layer formed thereon that is activated according to the bow measurement of the at least one of the wafer and the chiplet.

Abstract: A method of patterning a substrate includes forming a hardmask over an underlying layer supported by a substrate, forming antispacer trenches over the hardmask, and forming fully self-aligned vias (FSAVs) extending from the hardmask into the underlying layer. The hardmask includes hardmask line features defining hardmask trenches extending in a first direction. The antispacer trenches extend in a second direction nonparallel to the first direction. The FSAVs extend into the underlying layer at intersections of the hardmask trenches and the antispacer trenches. The FSAVs are self-aligned on two sides by sidewalls of the hardmask trenches and self-aligned on the remaining sides by sidewalls of the antispacer trenches.

Abstract: A method of processing a substrate, including generating a mask density map based on a photomask, the mask density map spatially mapping transparent regions of the photomask and blocking regions of the photomask that block radiation at a predetermined wavelength; generating a flare map based on the mask density map, the flare map spatially indicating a projected amount of received radiation in excess of a desired amount of radiation at each coordinate location on the photomask; and generating a critical dimension modification map based on the flare map, the critical dimension modification map including a modification energy dosage for each coordinate location on the photomask.

Abstract: A lighting apparatus a first group of at least one first solid state emitter, each first solid state emitter including a first light emitting diode (“LED”) that, when excited, emits light having a peak wavelength in a range between about 440 nm and about 475 nm, and a second group of at least one second solid state emitter, each second solid state emitter comprising a second LED that, when excited, emits light having a peak wavelength in a range between about 390 nm and about 415 nm. Between about 2% and about 15% of a spectral power of light emitted from the lighting apparatus is light having wavelengths in the range between about 390 nm and about 415 nm.

Abstract: A lighting apparatus a first group of at least one first solid state emitter, each first solid state emitter including a first light emitting diode (“LED”) that, when excited, emits light having a peak wavelength in a range between about 440 nm and about 475 nm, and a second group of at least one second solid state emitter, each second solid state emitter comprising a second LED that, when excited, emits light having a peak wavelength in a range between about 390 nm and about 415 nm. Between about 2% and about 15% of a spectral power of light emitted from the lighting apparatus is light having wavelengths in the range between about 390 nm and about 415 nm.

Abstract: A method of designing a standard cell layout includes determining a performance metric for the standard cell layout and executing an artificial intelligence (AI) algorithm. The executing of the AI algorithm includes extracting out a parameter of the standard cell layout having a different weighting with respect to optimizing the performance metric, adjusting the parameters of the standard cell layout, evaluating the performance metric based on the adjusted parameter of the standard cell layout, and continuing to adjust the one or more parameters until the performance metric reaches a desired value.

Abstract: A method includes providing a carrier substrate having a die bonded thereto, where the die includes a first alignment mark on a first surface. The method includes positioning a target substrate with a second surface on a substrate stage, where the target substrate includes a second alignment mark on the second surface. The method includes positioning the carrier substrate with respect to a die handler, where the die handler includes a third alignment mark. The method includes coupling the die to the die handler, where the step of coupling includes aligning the first alignment mark with the third alignment mark. The method includes positioning the coupled die and the die handler over the target substrate, where the step of positioning includes aligning the second alignment mark with at least one of the first alignment mark and the third alignment mark. The method includes bonding the first surface with the second surface.

Abstract: A process includes forming, over a dielectric layer, a hardmask stack including a first layer below a second layer below a third layer below a fourth layer. The first and third layers include a different hardmask material from the second and fourth layers. A trench pattern including sidewall spacer structures is formed over the hardmask stack. The fourth layer is etched in a first region. The fourth and third layers are etched in a second region. The fourth and third layers are etched in a third region. The fourth layer is etched in a fourth region. The second and first layers are etched in the second and third regions. The third layer is etched in the first and fourth regions. In the dielectric layer, trenches are formed in the first and fourth regions, and via openings, deeper than the trenches, are formed in the second and third regions.

Abstract: A method of patterning a substrate, where the method includes: forming first structures over a memorization layer, the first structures including a first row of lines that are parallel with each other and spaced apart from each other; executing a first anti-spacer formation process to form first trenches along sidewalls of the first structures and sidewalls of a first fill material, the first trenches defining a first etch pattern; transferring the first etch pattern into the memorization layer and removing materials above the memorization layer; forming second structures over the memorization layer, the second structures including a second row of lines that are parallel with each other and spaced apart, placement of the second row of lines being shifted relative to the first row of lines; executing a second anti-spacer formation process to form second trenches formed along sidewalls of the second structures and sidewalls of a second fill material, the second trenches defining a second etch pattern; and trans

Abstract: A lighting apparatus a first group of at least one first solid state emitter, each first solid state emitter including a first light emitting diode (“LED”) that, when excited, emits light having a peak wavelength in a range between about 440 nm and about 475 nm, and a second group of at least one second solid state emitter, each second solid state emitter comprising a second LED that, when excited, emits light having a peak wavelength in a range between about 390 nm and about 415 nm. Between about 2% and about 15% of a spectral power of light emitted from the lighting apparatus is light having wavelengths in the range between about 390 nm and about 415 nm.

Abstract: A lighting apparatus a first group of at least one first solid state emitter, each first solid state emitter including a first light emitting diode (“LED”) that, when excited, emits light having a peak wavelength in a range between about 440 nm and about 475 nm, and a second group of at least one second solid state emitter, each second solid state emitter comprising a second LED that, when excited, emits light having a peak wavelength in a range between about 390 nm and about 415 nm. Between about 2% and about 15% of a spectral power of light emitted from the lighting apparatus is light having wavelengths in the range between about 390 nm and about 415 nm.