Patents by Inventor David Richard Esler

David Richard Esler has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11950394
    Abstract: The disclosure relates to an apparatus and method for liquid cooling of an electronic component. A housing includes an insertion slot and defines at least one component chamber for carrying the electronic component. A fluid inlet and fluid outlet are provided on the housing. A liquid coolant circuit passes through the housing at least from the inlet to the outlet.
    Type: Grant
    Filed: October 12, 2021
    Date of Patent: April 2, 2024
    Assignee: GE Aviation Systems LLC
    Inventors: Brian Magann Rush, Christopher James Kapusta, David Richard Esler, Liang Yin, Richard Anthony Eddins, Judd Everett Swanson, Liqiang Yang
  • Publication number: 20230420901
    Abstract: The disclosure relates to an apparatus for connecting an electronic component to a conductor. A housing includes at least one slot and defines at least one component chamber for carrying the electronic component. A liquid coolant can pass through the housing. A pair of conductive members extends from the housing through the at least one slot and can be releasably inserted into a channel defined in a support assembly. The support assembly facilitates an electrical connection between the conductive members and corresponding conductive contact members connected to a respective power supply or electrical load. The support assembly can provide an inward sealing force to a seal on the housing circumscribing the pair of conductive members.
    Type: Application
    Filed: June 22, 2022
    Publication date: December 28, 2023
    Inventors: Christopher James Kapusta, David Richard Esler, Arun Virupaksha Gowda, Brian Magann Rush, Liang Yin, Richard Anthony Eddins, Liqiang Yang, Judd Everett Swanson
  • Publication number: 20230304879
    Abstract: A sensing element having improved temperature and pressure characteristics including at least one acoustic sensing device formed mainly from a silicon substrate and having a microelectromechanical system without the use of quartz or polymer, wherein the at least one acoustic sensing device detects a torque associated with a metal object subject to said torque, and a high temperature bonding surface for directly connecting the sensing element to the metal object via a high temperature connecting processes comprising at least one of soldering, metalizing and/or brazing, without the need for a polymer adhesive. Related sensors using such sensing elements and methods are also disclosed herein.
    Type: Application
    Filed: March 23, 2022
    Publication date: September 28, 2023
    Inventors: Robert James MacDonald, Yizhen Lin, Nicholas G. Yost, David Richard Esler
  • Publication number: 20230273160
    Abstract: A system includes a sensor comprising a sensor bonding layer disposed on a surface of the sensor, wherein the sensor bonding layer is a metallic alloy. An inlay includes a planar outer surface, wherein the inlay may be disposed on a curved surface of a structure. A structure bonding layer may be disposed on the planar outer surface of the inlay, wherein the structure bonding layer is a metallic alloy. The sensor bonding layer is coupled to the structure bonding layer via a metallic joint, and the sensor is configured to sense data of the structure through the metallic joint, the structure bonding layer, and the sensor bonding layer. The inlay comprises at least one of a modulus of elasticity, a shape, a thickness, and a size configured to reduce strain transmitted to the sensor.
    Type: Application
    Filed: April 14, 2023
    Publication date: August 31, 2023
    Applicant: General Electric Company
    Inventors: Joseph Alfred Iannotti, Christopher James Kapusta, David Richard Esler
  • Patent number: 11630086
    Abstract: A system includes a sensor comprising a sensor bonding layer disposed on a surface of the sensor, wherein the sensor bonding layer is a metallic alloy. An inlay includes a planar outer surface, wherein the inlay may be disposed on a curved surface of a structure. A structure bonding layer may be disposed on the planar outer surface of the inlay, wherein the structure bonding layer is a metallic alloy. The sensor bonding layer is coupled to the structure bonding layer via a metallic joint, and the sensor is configured to sense data of the structure through the metallic joint, the structure bonding layer, and the sensor bonding layer. The inlay comprises at least one of a modulus of elasticity, a shape, a thickness, and a size configured to reduce strain transmitted to the sensor.
    Type: Grant
    Filed: June 29, 2021
    Date of Patent: April 18, 2023
    Assignee: General Electric Company
    Inventors: Joseph Alfred Iannotti, Christopher James Kapusta, David Richard Esler
  • Publication number: 20230114057
    Abstract: The disclosure relates to an apparatus and method for liquid cooling of an electronic component. A housing includes an insertion slot and defines at least one component chamber for carrying the electronic component. A fluid inlet and fluid outlet are provided on the housing. A liquid coolant circuit passes through the housing at least from the inlet to the outlet.
    Type: Application
    Filed: October 12, 2021
    Publication date: April 13, 2023
    Inventors: Brian Magann Rush, Christopher James Kapusta, David Richard Esler, Liang Yin, Richard Anthony Eddins, Judd Everett Swanson, Liqiang Yang
  • Publication number: 20230020337
    Abstract: An electrical component and method for manufacturing the electrical component with a substrate a conductor stack having multiple layers and including at least one electrically conductive path. The conductor stack mounted to the substrate with a dielectric passivation stack encasing at least a portion of the conductor stack.
    Type: Application
    Filed: September 21, 2022
    Publication date: January 19, 2023
    Inventors: Cheng-Po Chen, Reza Ghandi, David Richard Esler, David Mulford Shaddock, Emad Andarawis Andarawis, Liang Yin
  • Patent number: 11551993
    Abstract: A power overlay (POL) module includes a semiconductor device having a first side and an opposing second side, a dielectric sheet having a first side coupled to the semiconductor device second side, and an opposing second side, the dielectric sheet defining an aperture therethrough. The POL module also includes a first conductive layer disposed on the second side of the dielectric sheet and electrically coupled through the aperture to the semiconductor device second surface, a first conductive plate having a first side, and an opposing second side coupled to the first surface of the semiconductor device. The POL module further includes a first heat sink coupled the first side of the conductive plate and a first thermal interface layer disposed between the first conductive plate and the first heat sink.
    Type: Grant
    Filed: August 28, 2020
    Date of Patent: January 10, 2023
    Assignee: GE Aviation Systems LLC
    Inventors: David Richard Esler, Christopher James Kapusta, Arun V. Gowda, Weijun Yin, Liqiang Yang, Richard Anthony Eddins
  • Patent number: 11538769
    Abstract: A semiconductor device is provided. The semiconductor device includes an electric field (E-field) suppression layer formed over a termination region. The E-field suppression layer is patterned with openings over metal contact areas. The E-field suppression layer has a thickness such that an electric field strength above the E-field suppression layer is below a dielectric strength of an adjacent material when the semiconductor device is operating at or below a maximum voltage.
    Type: Grant
    Filed: December 14, 2018
    Date of Patent: December 27, 2022
    Assignee: General Electric Company
    Inventors: Stephen Daley Arthur, Liangchun Yu, Nancy Cecelia Stoffel, David Richard Esler, Christopher James Kapusta
  • Patent number: 11482449
    Abstract: An electrical component and method for manufacturing the electrical component with a substrate a conductor stack having multiple layers and including at least one electrically conductive path. The conductor stack mounted to the substrate with a dielectric passivation stack encasing at least a portion of the conductor stack.
    Type: Grant
    Filed: August 3, 2020
    Date of Patent: October 25, 2022
    Assignee: General Electric Company
    Inventors: Cheng-Po Chen, Reza Ghandi, David Richard Esler, David Mulford Shaddock, Emad Andarawis Andarawis, Liang Yin
  • Patent number: 11328973
    Abstract: A device comprises: a high temperature semiconductor device comprising a first surface, wherein the high temperature semiconductor device comprises an active area and a termination area disposed adjacent to the active area; an inorganic dielectric insulating layer disposed on the first surface, wherein the inorganic dielectric insulating layer fills a volume extending over an entirety of the termination area and comprises a thickness greater than or equal to 25 ?m and less than or equal to 500 ?m; and an electrical connector connecting the active area of the high temperature semiconductor device to an additional component of the device.
    Type: Grant
    Filed: June 26, 2020
    Date of Patent: May 10, 2022
    Assignee: General Electric Company
    Inventors: David Richard Esler, Emad A. Andarawis
  • Patent number: 11289444
    Abstract: A sensor assembly includes a die substrate and a metalized layer formed on the die substrate. The metalized layer is formed of a first metal material and includes a bonding pad to facilitate electrically coupling the sensor assembly to a sensor system. A remetalized bump is formed on the bonding pad of a second metal material and is electrically coupled to the metalized layer. An adhesive is applied to the remetalized bump and facilitates mechanically coupling the sensor assembly to the sensor system.
    Type: Grant
    Filed: December 13, 2019
    Date of Patent: March 29, 2022
    Assignee: General Electric Company
    Inventors: David Richard Esler, Nancy Cecelia Stoffel
  • Publication number: 20220070996
    Abstract: A power overlay (POL) module includes a semiconductor device having a first side and an opposing second side, a dielectric sheet having a first side coupled to the semiconductor device second side, and an opposing second side, the dielectric sheet defining an aperture therethrough. The POL module also includes a first conductive layer disposed on the second side of the dielectric sheet and electrically coupled through the aperture to the semiconductor device second surface, a first conductive plate having a first side, and an opposing second side coupled to the first surface of the semiconductor device. The POL module further includes a first heat sink coupled the first side of the conductive plate and a first thermal interface layer disposed between the first conductive plate and the first heat sink.
    Type: Application
    Filed: August 28, 2020
    Publication date: March 3, 2022
    Inventors: David Richard Esler, Christopher James Kapusta, Arun V. Gowda, Weijun Yin, Liqiang Yang, Richard Anthony Eddins
  • Publication number: 20220037201
    Abstract: An electrical component and method for manufacturing the electrical component with a substrate a conductor stack having multiple layers and including at least one electrically conductive path. The conductor stack mounted to the substrate with a dielectric passivation stack encasing at least a portion of the conductor stack.
    Type: Application
    Filed: August 3, 2020
    Publication date: February 3, 2022
    Inventors: Cheng-Po Chen, Reza Ghandi, David Richard Esler, David Mulford Shaddock, Emad Andarawis Andarawis, Liang Yin
  • Publication number: 20210407878
    Abstract: A device comprises: a high temperature semiconductor device comprising a first surface, wherein the high temperature semiconductor device comprises an active area and a termination area disposed adjacent to the active area; an inorganic dielectric insulating layer disposed on the first surface, wherein the inorganic dielectric insulating layer fills a volume extending over an entirety of the termination area and comprises a thickness greater than or equal to 25 ?m and less than or equal to 500 ?m; and an electrical connector connecting the active area of the high temperature semiconductor device to an additional component of the device.
    Type: Application
    Filed: June 26, 2020
    Publication date: December 30, 2021
    Applicant: GENERAL ELECTRIC COMPANY
    Inventors: David Richard Esler, Emad A. Andarawis
  • Publication number: 20210325348
    Abstract: A system includes a sensor comprising a sensor bonding layer disposed on a surface of the sensor, wherein the sensor bonding layer is a metallic alloy. An inlay includes a planar outer surface, wherein the inlay may be disposed on a curved surface of a structure. A structure bonding layer may be disposed on the planar outer surface of the inlay, wherein the structure bonding layer is a metallic alloy. The sensor bonding layer is coupled to the structure bonding layer via a metallic joint, and the sensor is configured to sense data of the structure through the metallic joint, the structure bonding layer, and the sensor bonding layer. The inlay comprises at least one of a modulus of elasticity, a shape, a thickness, and a size configured to reduce strain transmitted to the sensor.
    Type: Application
    Filed: June 29, 2021
    Publication date: October 21, 2021
    Applicant: General Electric Company
    Inventors: Joseph Alfred Iannotti, Christopher James Kapusta, David Richard Esler
  • Patent number: 11079359
    Abstract: A system includes a structure bonding layer and a sensor. The structure bonding layer is disposed on a structure. The structure bonding layer is a metallic alloy. The sensor includes a non-metallic wafer and a sensor bonding layer disposed on a surface of the non-metallic wafer. The sensor bonding layer is a metallic alloy. The sensor bonding layer is coupled to the structure bonding layer via a metallic joint, and the sensor is configured to sense data of the structure through the metallic joint, the structure bonding layer, and the sensor bonding layer.
    Type: Grant
    Filed: December 19, 2019
    Date of Patent: August 3, 2021
    Assignee: General Electric Company
    Inventors: Joseph Alfred Iannotti, Christopher James Kapusta, David Richard Esler
  • Publication number: 20210183808
    Abstract: A sensor assembly includes a die substrate and a metalized layer formed on the die substrate. The metalized layer is formed of a first metal material and includes a bonding pad to facilitate electrically coupling the sensor assembly to a sensor system. A re-metalized bump is formed on the bonding pad of a second metal material and is electrically coupled to the metalized layer. An adhesive is applied to the re-metalized bump and facilitates mechanically coupling the sensor assembly to the sensor system.
    Type: Application
    Filed: December 13, 2019
    Publication date: June 17, 2021
    Inventors: David Richard Esler, Nancy Cecelia Stoffel
  • Patent number: 10892237
    Abstract: Methods of fabricating a semiconductor device are provided. The method includes providing a plurality of semiconductor devices. The method further includes disposing a dielectric dry film on the plurality of semiconductor devices, wherein the dielectric dry film is patterned such that openings in the patterned dielectric dry film are aligned with conductive pads of each of the plurality of semiconductor devices.
    Type: Grant
    Filed: December 14, 2018
    Date of Patent: January 12, 2021
    Assignee: General Electric Company
    Inventors: Stephen Daley Arthur, Liangchun Yu, Nancy Cecelia Stoffel, David Richard Esler, Christopher James Kapusta
  • Publication number: 20200194388
    Abstract: Methods of fabricating a semiconductor device are provided. The method includes providing a plurality of semiconductor devices. The method further includes disposing a dielectric dry film on the plurality of semiconductor devices, wherein the dielectric dry film is patterned such that openings in the patterned dielectric dry film are aligned with conductive pads of each of the plurality of semiconductor devices.
    Type: Application
    Filed: December 14, 2018
    Publication date: June 18, 2020
    Inventors: Stephen Daley Arthur, Liangchun Yu, Nancy Cecelia Stoffel, David Richard Esler, Christopher James Kapusta