Abstract: A threaded insert with a replaceable nut element allows a user to replace only the nut element of the threaded insert rather than the entire threaded insert. The threaded insert includes an insertable housing, a replaceable nut, a retaining mechanism, and an attachment mechanism. The insertable housing allows the threaded insert to be engaged within a wall structure and is used to contain the replaceable nut. The replaceable nut allows the threaded insert to be engaged by a fastener such as a screw or bolt. The attachment mechanism allows the replaceable nut to be attached within and detached from the insertable housing. The retaining mechanism further secures the replaceable nut within the insertable housing and also prevents the replaceable nut from rotating within the insertable housing.

Abstract: Embodiments provide a spacecraft airlock system. Embodiments provide a method and apparatus for attaching space exposed payloads to a space station. The spacecraft airlock system provides a defined volume of space payload to the international space station. The airlock further includes a means of attaching to a space station, a closed structure attached to said means, said means of attaching is capable of robotic manipulation, and a cooling system for cooling payload components within said closed structure.

Abstract: Embodiments provide a spacecraft airlock system. Embodiments provide a method and apparatus for attaching space exposed payloads to a space station. The spacecraft airlock system provides a defined volume of space payload to the international space station. The airlock further includes a means of attaching to a space station, a closed structure attached to said means, said means of attaching is capable of robotic manipulation, and a cooling system for cooling payload components within said closed structure.

Abstract: A power management integrated circuit (PMIC) capable of operating, in memory systems, as a master control in power management in some situations and operating as a slave control in power management in other situations. For example, when used in a memory system operating on a SATA bus, the PMIC assumes the master control by monitoring the bus signals for entering or existing a sleep mode or a power shutdown mode, communicating to the controller of the memory system to prepare for the respective mode, and when ready, adjusting power states for the mode changes. For example, when used in a memory system operating on a PCIe bus, the PMIC assumes the slave control during a normal mode and a sleep mode, but the master control when the memory system is in a power disable mode in which the controller of the memory system is powered off.

Abstract: Disclosed are devices and methods for protecting the register file of a power management integrated circuit (PMIC). In one embodiment, a device is disclosed comprising: a register file comprising a plurality of a registers, at least one register in the register file containing a write register bit (WRB); and an interface configured to receive messages from a host application, the messages including a WRB enablement signal, wherein the device is configured to enable writing to the register file in response to receiving the WRB enablement signal over the interface, write data in response to write messages while writing to the register file is enabled, and disable writing to the register file in response to receiving a stop bit over the interface.

Abstract: A power management circuit receives power from a host and a backup power supply in parallel and uses power from at least one of the host and the backup power supply to operate voltage regulators for a memory system. An enable signal is generated based on whether or not the voltage regulators are powered. The enable signal can be used to keep the backup power supply on while the memory system is in operation. In response to absence of power from the host, the circuit generates an interrupt signal causing the memory system to shut down safely without data loss.

Abstract: A memory system having a non-volatile memory and a power management integrated circuit (PMIC) that has a voltage regulator to apply a voltage on the non-volatile memory during normal operations. During a shutdown process, the PMIC has a bleeder that is activated to reduce the voltage applied on the non-volatile memory to a level that is below a programmable threshold, before allowing the memory system to restart again. During the bleeding operation, a comparator of the PMIC compares the voltage applied to the non-volatile memory and the threshold to determine whether the shutdown process can be terminated for a restart.

Abstract: A power management circuit receives power from a host and a backup power supply in parallel and uses power from at least one of the host and the backup power supply to operate voltage regulators for a memory system. An enable signal is generated based on whether or not the voltage regulators are powered. The enable signal can be used to keep the backup power supply on while the memory system is in operation. In response to absence of power from the host, the circuit generates an interrupt signal causing the memory system to shut down safely without data loss.

Abstract: Disclosed are devices and methods for protecting the register file of a power management integrated circuit (PMIC). In one embodiment, a device is disclosed comprising: a register file comprising a plurality of a registers, at least one register in the register file containing a write register bit (WRB); and an interface configured to receive messages from a host application, the messages including a WRB enablement signal, wherein the device is configured to enable writing to the register file in response to receiving the WRB enablement signal over the interface, write data in response to write messages while writing to the register file is enabled, and disable writing to the register file in response to receiving a stop bit over the interface.

Abstract: A threaded insert with a replaceable nut element allows a user to replace only the nut element of the threaded insert rather than the entire threaded insert. The threaded insert includes an insertable housing, a replaceable nut, a retaining mechanism, and an attachment mechanism. The insertable housing allows the threaded insert to be engaged within a wall structure and is used to contain the replaceable nut. The replaceable nut allows the threaded insert to be engaged by a fastener such as a screw or bolt. The attachment mechanism allows the replaceable nut to be attached within and detached from the insertable housing. The retaining mechanism further secures the replaceable nut within the insertable housing and also prevents the replaceable nut from rotating within the insertable housing.

Abstract: Disclosed is a power management integrated circuit with embedded address resolution protocol functionality. In one embodiment, a device is disclosed comprising a data storage device; and an address resolution protocol (ARP) state machine communicatively coupled to the data storage device and included within a power management integrated circuit (PMIC), the ARP state machine configured to assign an address to the data storage device and validate requests for data stored in the data storage device received over a bus.

Abstract: Disclosed is a power management integrated circuit including dual one-time programmable memory banks and methods for controlling the same. In one embodiment, the power management integrated circuit (PMIC) includes a first one-time programmable (OTP) memory bank; a second OTP memory bank; and access control logic, communicatively coupled to the first OTP bank and the second OTP bank, the access control logic configured to: utilize the first OTP memory bank for operation of the PMIC upon detecting that the second OTP memory bank is empty, write data to the second OTP memory bank in response to a write request from a host application if the second OTP memory bank is not empty, and utilize the second OTP memory bank for operation of the PMIC upon detecting that the second OTP memory bank is not empty.

Abstract: The present invention provides compositions derived from cranberry including xyloglucan and pectic oligosaccharides, and iridoid terpene glycosides. These compositions can be used in conjunction with antibiotics to synergistically kill bacterial persister cells and inhibit bacterial quiescent phenotypes, thereby improving treatment outcomes in recurrent and other infections.

Abstract: A power management circuit that has multiple sets of circuits to provide certain same power management functionalities in different power modes, such as voltage, current and temperature sensing and/or measuring, generating of reference states or biases to effectuate circuit protection in various conditions, such as under voltages, over voltages, etc. One set of circuits is configured to operate during a normal mode and is optimized for performance, speed and/or accuracy. Another set of circuits is configured to operate during a sleep mode and is optimized for reduced power consumption where the performance, speed and/or accuracy may be inferior to the circuits for the normal mode but the functionality is maintained within the low power consumption constraint.

Abstract: A memory system having a non-volatile memory and a power management integrated circuit (PMIC) that has a voltage regulator to apply a voltage on the non-volatile memory during normal operations. During a shutdown process, the PMIC has a bleeder that is activated to reduce the voltage applied on the non-volatile memory to a level that is below a programmable threshold, before allowing the memory system to restart again. During the bleeding operation, a comparator of the PMIC compares the voltage applied to the non-volatile memory and the threshold to determine whether the shutdown process can be terminated for a restart.

Abstract: A power management circuit that has multiple sets of circuits to provide certain same power management functionalities in different power modes, such as voltage, current and temperature sensing and/or measuring, generating of reference states or biases to effectuate circuit protection in various conditions, such as under voltages, over voltages, etc. One set of circuits is configured to operate during a normal mode and is optimized for performance, speed and/or accuracy. Another set of circuits is configured to operate during a sleep mode and is optimized for reduced power consumption where the performance, speed and/or accuracy may be inferior to the circuits for the normal mode but the functionality is maintained within the low power consumption constraint.

Abstract: A memory system having a non-volatile memory and a power management integrated circuit (PMIC) that has a voltage regulator to apply a voltage on the non-volatile memory during normal operations. During a shutdown process, the PMIC has a bleeder that is activated to reduce the voltage applied on the non-volatile memory to a level that is below a programmable threshold, before allowing the memory system to restart again. During the bleeding operation, a comparator of the PMIC compares the voltage applied to the non-volatile memory and the threshold to determine whether the shutdown process can be terminated for a restart.

Abstract: A power management integrated circuit (PMIC) capable of operating, in memory systems, as a master control in power management in some situations and operating as a slave control in power management in other situations. For example, when used in a memory system operating on a SATA bus, the PMIC assumes the master control by monitoring the bus signals for entering or existing a sleep mode or a power shutdown mode, communicating to the controller of the memory system to prepare for the respective mode, and when ready, adjusting power states for the mode changes. For example, when used in a memory system operating on a PCIe bus, the PMIC assumes the slave control during a normal mode and a sleep mode, but the master control when the memory system is in a power disable mode in which the controller of the memory system is powered off.

Abstract: Disclosed is an improved load switch driver for Power Management Integrated Circuit (PMIC) devices. In one embodiment, a PMIC is disclosed comprising a gate driver, the gate driver connected to the gate of a switch; an operation frequency generator connected to the gate driver and configured to supply a periodic voltage to the gate driver; and a voltage sensor, the voltage sensor connected to the operation frequency generator and the source of the switch, the voltage sensor configured to monitor a drain-source voltage of the switch and lower the frequency of the operation frequency generator to a second frequency in response to detecting a collapse of the drain-source voltage.