Patents by Inventor David S. Wolpert
David S. Wolpert has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10248749Abstract: Examples of techniques for automated attribute propagation and hierarchical consistency checking are disclosed. In one example implementation according to aspects of the present disclosure, a computer-implemented method may include: detecting, by a processor, a non-standard extension during convergence of an integrated circuit logic design; propagating, by the processor, the non-standard extension to each level of a plurality of hierarchies of the integrated circuit design for which a net utilizes a special constraint; and verifying, by the processor, a hierarchy consistency across each level of the plurality of hierarchies.Type: GrantFiled: February 15, 2018Date of Patent: April 2, 2019Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Robert M. Averill, III, Erwin Behnen, David S. Wolpert
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Patent number: 10223487Abstract: Examples of techniques for automated attribute propagation and hierarchical consistency checking are disclosed. In one example implementation according to aspects of the present disclosure, a computer-implemented method may include: detecting, by a processor, a non-standard extension during convergence of an integrated circuit logic design; propagating, by the processor, the non-standard extension to each level of a plurality of hierarchies of the integrated circuit design for which a net utilizes a special constraint; and verifying, by the processor, a hierarchy consistency across each level of the plurality of hierarchies.Type: GrantFiled: February 13, 2017Date of Patent: March 5, 2019Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Robert M. Averill, III, Erwin Behnen, David S. Wolpert
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Patent number: 10114649Abstract: An instruction control interface is provided for automatically controlling assigning of one or more instructions for processing by one or more processor cores of a computing device. The control interface separately monitors temperatures of multiple logic units within each processor core of the processor core(s) of the computing device, and controls assigning of one or more instructions for processing by a particular processor core(s) based, at least in part, on the separately monitored temperatures of the multiple logic units within the processor core(s).Type: GrantFiled: May 26, 2015Date of Patent: October 30, 2018Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: K. Paul Muller, David S. Wolpert
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Publication number: 20180173817Abstract: Examples of techniques for automated attribute propagation and hierarchical consistency checking are disclosed. In one example implementation according to aspects of the present disclosure, a computer-implemented method may include: detecting, by a processor, a non-standard extension during convergence of an integrated circuit logic design; propagating, by the processor, the non-standard extension to each level of a plurality of hierarchies of the integrated circuit design for which a net utilizes a special constraint; and verifying, by the processor, a hierarchy consistency across each level of the plurality of hierarchies.Type: ApplicationFiled: February 15, 2018Publication date: June 21, 2018Inventors: Robert M. Averill, III, Erwin Behnen, David S. Wolpert
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Patent number: 9977851Abstract: Examples of techniques for automated attribute propagation and hierarchical consistency checking are disclosed. In one example implementation according to aspects of the present disclosure, a computer-implemented method may include: detecting, by a processor, a non-standard extension during convergence of an integrated circuit logic design; propagating, by the processor, the non-standard extension to each level of a plurality of hierarchies of the integrated circuit design for which a net utilizes a special constraint; and verifying, by the processor, a hierarchy consistency across each level of the plurality of hierarchies.Type: GrantFiled: November 16, 2017Date of Patent: May 22, 2018Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Robert M. Averill, III, Erwin Behnen, David S. Wolpert
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Patent number: 9971861Abstract: Aspects include techniques for selective boundary overlay insertion for hierarchical circuit design. A method may include determining, by a processing device, a block type of a child block. The method may further include electively inserting, by the processing device, at least one of an instantiated boundary overlay and a merged boundary overlay into the hierarchical circuit design based on the block type of the child block. The instantiated boundary overlay enables a parent block to pass a testing at an out-of-context level, and the merged boundary overlay enables the parent block to continue to pass the testing when the child block is inserted into the parent block associated with the child block.Type: GrantFiled: February 10, 2016Date of Patent: May 15, 2018Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Erwin Behnen, Michael S. Gray, Matthew T. Guzowski, David S. Wolpert
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Publication number: 20180075171Abstract: Examples of techniques for automated attribute propagation and hierarchical consistency checking are disclosed. In one example implementation according to aspects of the present disclosure, a computer-implemented method may include: detecting, by a processor, a non-standard extension during convergence of an integrated circuit logic design; propagating, by the processor, the non-standard extension to each level of a plurality of hierarchies of the integrated circuit design for which a net utilizes a special constraint; and verifying, by the processor, a hierarchy consistency across each level of the plurality of hierarchies.Type: ApplicationFiled: November 16, 2017Publication date: March 15, 2018Inventors: Robert M. Averill, III, Erwin Behnen, David S. Wolpert
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Publication number: 20180046734Abstract: Examples of techniques for automated attribute propagation and hierarchical consistency checking are disclosed. In one example implementation according to aspects of the present disclosure, a computer-implemented method may include: detecting, by a processor, a non-standard extension during convergence of an integrated circuit logic design; propagating, by the processor, the non-standard extension to each level of a plurality of hierarchies of the integrated circuit design for which a net utilizes a special constraint; and verifying, by the processor, a hierarchy consistency across each level of the plurality of hierarchies.Type: ApplicationFiled: February 13, 2017Publication date: February 15, 2018Inventors: Robert M. Averill, III, Erwin Behnen, David S. Wolpert
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Publication number: 20180046741Abstract: Examples of techniques for automated attribute propagation and hierarchical consistency checking are disclosed. In one example implementation according to aspects of the present disclosure, a computer-implemented method may include: detecting, by a processor, a non-standard extension during convergence of an integrated circuit logic design; propagating, by the processor, the non-standard extension to each level of a plurality of hierarchies of the integrated circuit design for which a net utilizes a special constraint; and verifying, by the processor, a hierarchy consistency across each level of the plurality of hierarchies.Type: ApplicationFiled: August 11, 2016Publication date: February 15, 2018Inventors: Robert M. Averill, III, Erwin Behnen, David S. Wolpert
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Patent number: 9892222Abstract: Examples of techniques for automated attribute propagation and hierarchical consistency checking are disclosed. In one example implementation according to aspects of the present disclosure, a computer-implemented method may include: detecting, by a processor, a non-standard extension during convergence of an integrated circuit logic design; propagating, by the processor, the non-standard extension to each level of a plurality of hierarchies of the integrated circuit design for which a net utilizes a special constraint; and verifying, by the processor, a hierarchy consistency across each level of the plurality of hierarchies.Type: GrantFiled: August 11, 2016Date of Patent: February 13, 2018Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Robert M. Averill, III, Erwin Behnen, David S. Wolpert
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Publication number: 20170228486Abstract: Aspects include techniques for selective boundary overlay insertion for hierarchical circuit design. A method may include determining, by a processing device, a block type of a child block. The method may further include electively inserting, by the processing device, at least one of an instantiated boundary overlay and a merged boundary overlay into the hierarchical circuit design based on the block type of the child block. The instantiated boundary overlay enables a parent block to pass a testing at an out-of-context level, and the merged boundary overlay enables the parent block to continue to pass the testing when the child block is inserted into the parent block associated with the child block.Type: ApplicationFiled: February 10, 2016Publication date: August 10, 2017Inventors: Erwin Behnen, Michael S. Gray, Matthew T. Guzowski, David S. Wolpert
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Patent number: 9728274Abstract: A technique is provided for system reliability. An input is received, and a computation operation on the input is repeated to generate multiple output values. The multiple output values are stored in a table along with a number of hits for each distinct output value in the multiple output values, and the number of hits indicates a number of times each distinct output value was generated by the repeating. A reliability circuit checks whether the number of hits for any one distinct output value meets a confidence threshold. Based on meeting the confidence threshold for the number of hits, the any one distinct output value is output. Based on the number of hits for the any one distinct output value not meeting the confidence threshold, the computation operation is continuously repeated on the input until the number of hits for the any one distinct output value meets the confidence threshold.Type: GrantFiled: September 30, 2014Date of Patent: August 8, 2017Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventor: David S. Wolpert
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Patent number: 9626220Abstract: A multiple processor core computer system interface assigns instructions to partially functional processor cores based on processing resources available in each partially functional core. Each processor core is labeled as fully functional, partially functional, or non-functional, and an indicator is provided for each partially functional processor core that shows what processing resources are available for a respective core. The indicators can be stored in memory after final test. The interface can monitor cores for changes in available resources and update respective indicators, such as by superseding an existing indicator with or creating a new indicator in read-write memory.Type: GrantFiled: January 13, 2015Date of Patent: April 18, 2017Assignee: International Business Machines CorporationInventors: Marcel Mitran, K. Paul Muller, William J. Rooney, Joran S. C. Siu, David S. Wolpert
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Publication number: 20160350117Abstract: An instruction control interface is provided for automatically controlling assigning of one or more instructions for processing by one or more processor cores of a computing device. The control interface separately monitors temperatures of multiple logic units within each processor core of the processor core(s) of the computing device, and controls assigning of one or more instructions for processing by a particular processor core(s) based, at least in part, on the separately monitored temperatures of the multiple logic units within the processor core(s).Type: ApplicationFiled: May 26, 2015Publication date: December 1, 2016Inventors: K. Paul MULLER, David S. WOLPERT
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Publication number: 20160203023Abstract: A multiple processor core computer system interface assigns instructions to partially functional processor cores based on processing resources available in each partially functional core. Each processor core is labeled as fully functional, partially functional, or non-functional, and an indicator is provided for each partially functional processor core that shows what processing resources are available for a respective core. The indicators can be stored in memory after final test. The interface can monitor cores for changes in available resources and update respective indicators, such as by superseding an existing indicator with or creating a new indicator in read-write memory.Type: ApplicationFiled: January 13, 2015Publication date: July 14, 2016Inventors: Marcel Mitran, K. Paul Muller, William J. Rooney, Joran S.C. Siu, David S. Wolpert
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Patent number: 9384857Abstract: A technique is provided for system reliability. An input is received, and a computation operation on the input is repeated to generate multiple output values. The multiple output values are stored in a table along with a number of hits for each distinct output value in the multiple output values, and the number of hits indicates a number of times each distinct output value was generated by the repeating. A reliability circuit checks whether the number of hits for any one distinct output value meets a confidence threshold. Based on meeting the confidence threshold for the number of hits, the any one distinct output value is output. Based on the number of hits for the any one distinct output value not meeting the confidence threshold, the computation operation is continuously repeated on the input until the number of hits for the any one distinct output value meets the confidence threshold.Type: GrantFiled: April 30, 2014Date of Patent: July 5, 2016Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventor: David S. Wolpert
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Patent number: 9201727Abstract: A system for providing error detection or correction on a data bus includes one or more caches coupled to a central processing unit and to a hub by one or more buses. The system also includes a plurality of arrays, each array disposed on one of the buses. Each of the arrays includes a plurality of storage cells disposed in an insensitive direction and an error control mechanism configured to detect an error in the plurality of storage cells.Type: GrantFiled: January 15, 2013Date of Patent: December 1, 2015Assignee: International Business Machines CorporationInventors: William V. Huott, Kevin W. Kark, John G. Massey, K. Paul Muller, David L. Rude, David S. Wolpert
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Publication number: 20150317195Abstract: A technique is provided for system reliability. An input is received, and a computation operation on the input is repeated to generate multiple output values. The multiple output values are stored in a table along with a number of hits for each distinct output value in the multiple output values, and the number of hits indicates a number of times each distinct output value was generated by the repeating. A reliability circuit checks whether the number of hits for any one distinct output value meets a confidence threshold. Based on meeting the confidence threshold for the number of hits, the any one distinct output value is output. Based on the number of hits for the any one distinct output value not meeting the confidence threshold, the computation operation is continuously repeated on the input until the number of hits for the any one distinct output value meets the confidence threshold.Type: ApplicationFiled: April 30, 2014Publication date: November 5, 2015Applicant: International Business Machines CorporationInventor: David S. Wolpert
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Publication number: 20150318060Abstract: A technique is provided for system reliability. An input is received, and a computation operation on the input is repeated to generate multiple output values. The multiple output values are stored in a table along with a number of hits for each distinct output value in the multiple output values, and the number of hits indicates a number of times each distinct output value was generated by the repeating. A reliability circuit checks whether the number of hits for any one distinct output value meets a confidence threshold. Based on meeting the confidence threshold for the number of hits, the any one distinct output value is output. Based on the number of hits for the any one distinct output value not meeting the confidence threshold, the computation operation is continuously repeated on the input until the number of hits for the any one distinct output value meets the confidence threshold.Type: ApplicationFiled: September 30, 2014Publication date: November 5, 2015Inventor: David S. Wolpert
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Patent number: 9043683Abstract: A method for providing error detection and/or correction to an array of storage cells includes determining a sensitive direction and an insensitive direction of the storage cells and adding a first error control mechanism to the array of storage cells in the insensitive direction. The method also includes adding a second error control mechanism to the array of storage cells in the sensitive direction. The second error control mechanism has a higher Hamming distance than the first error control mechanism.Type: GrantFiled: January 23, 2013Date of Patent: May 26, 2015Assignee: International Business Machines CorporationInventors: William V. Huott, Kevin W. Kark, John G. Massey, K. Paul Muller, David L. Rude, David S. Wolpert