Abstract: A method for configuring the placement of a plurality of storage cells on an integrated circuit includes grouping the plurality of storage cells into a plurality of words, where each of the plurality of words is protected by an error control mechanism. The method also includes placing each of the storage cells on the integrated circuit such that a distance between any two of the storage cells belonging to one of the plurality of words is greater than a minimum distance. The minimum distance is configured such that a probability of any of the plurality of words experiencing multiple radiation induced errors is below a threshold value.

Abstract: A method for adding error detection, or error detection combined with error correction, to a plurality of register banks includes grouping the plurality of register banks into an array. The method also includes adding a first error control mechanism to the array in a first direction and adding a second error control mechanism to the array in a second direction. The method further includes adding a product code to the array, the product code including applying the second error control mechanism to a plurality of bits of the first error control mechanism.

Abstract: A method for providing error detection and/or correction to an array of storage cells includes determining a sensitive direction and an insensitive direction of the storage cells and adding a first error control mechanism to the array of storage cells in the insensitive direction. The method also includes adding a second error control mechanism to the array of storage cells in the sensitive direction. The second error control mechanism has a higher Hamming distance than the first error control mechanism.

Abstract: A system for providing error detection or correction on a data bus includes one or more caches coupled to a central processing unit and to a hub by one or more buses. The system also includes a plurality of arrays, each array disposed on one of the buses. Each of the arrays includes a plurality of storage cells disposed in an insensitive direction and an error control mechanism configured to detect an error in the plurality of storage cells.

Abstract: A method for adding error detection, or error detection combined with error correction, to a plurality of register banks includes grouping the plurality of register banks into an array. The method also includes adding a first error control mechanism to the array in a first direction and adding a second error control mechanism to the array in a second direction. The method further includes adding a product code to the array, the product code including applying the second error control mechanism to a plurality of bits of the first error control mechanism.

Abstract: A method for configuring the placement of a plurality of storage cells on an integrated circuit includes grouping the plurality of storage cells into a plurality of words, where each of the plurality of words is protected by an error control mechanism. The method also includes placing each of the storage cells on the integrated circuit such that a distance between any two of the storage cells belonging to one of the plurality of words is greater than a minimum distance. The minimum distance is configured such that a probability of any of the plurality of words experiencing multiple radiation induced errors is below a threshold value.

Abstract: A test circuit that compares test results between two tests with different local supply voltages is provided. The output of each stage of the logic circuits is stored in a first register of each test circuit. Each test is performed with a critical test vector and a local supply voltage that decreases from test to test. The outputs of successive tests are compared in each test circuit. The tests are performed iteratively with successive reduction in the value of the local supply voltage until at least one stage of the logic circuits produces non-matching results between the first and second register. The voltage immediately before producing such non-matching results is the minimum operational voltage for the local voltage island.

Abstract: A test circuit that compares test results between two tests with different local supply voltages is provided. The output of each stage of the logic circuits is stored in a first register of each test circuit. Each test is performed with a critical test vector and a local supply voltage that decreases from test to test. The outputs of successive tests are compared in each test circuit. The tests are performed iteratively with successive reduction in the value of the local supply voltage until at least one stage of the logic circuits produces non-matching results between the first and second register. The voltage immediately before producing such non-matching results is the minimum operational voltage for the local voltage island.