Patents by Inventor David Seo
David Seo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 10157989Abstract: A method of manufacturing a graphene electronic device may include forming a metal compound layer and a catalyst layer on a substrate, the catalyst layer including a metal element in the metal compound layer, growing a graphene layer on the catalyst layer, and converting the catalyst layer into a portion of the metal compound layer.Type: GrantFiled: May 23, 2012Date of Patent: December 18, 2018Assignee: Samsung Electronics Co., Ltd.Inventors: Chang Seung Lee, Sang Wook Kim, Seong Jun Park, David Seo, Young Jun Yun, Yung Hee Lee
-
Patent number: 10141407Abstract: According to example embodiments, a graphene device includes a first electrode, a first insulation layer on the first electrode, an information storage layer on the first insulation layer, a second insulation layer on the information storage layer, a graphene layer on the second insulation layer, a third insulation layer on a first region of the graphene layer, a second electrode on the third insulation layer, and a third electrode on a second region of the graphene layer.Type: GrantFiled: October 3, 2014Date of Patent: November 27, 2018Assignee: Samsung Electronics Co., Ltd.Inventors: David Seo, Ho-jung Kim, In-kyeong Yoo, Myoung-jae Lee, Seong-ho Cho
-
Patent number: 9929239Abstract: The present disclosure relates to a semiconductor device including an oxygen gettering layer between a group III-V compound semiconductor layer and a dielectric layer, and a method of fabricating the semiconductor device. The semiconductor device may include a compound semiconductor layer; a dielectric layer disposed on the compound semiconductor layer; and an oxygen gettering layer interposed between the compound semiconductor layer and the dielectric layer. The oxygen gettering layer includes a material having a higher oxygen affinity than a material of the compound semiconductor layer.Type: GrantFiled: February 23, 2016Date of Patent: March 27, 2018Assignee: Samsung Electronics Co., Ltd.Inventors: Dong-soo Lee, Myoung-jae Lee, Seong-ho Cho, Mohammad Rakib Uddin, David Seo, Moon-seung Yang, Sang-moon Lee, Sung-hun Lee, Ji-hyun Hur, Eui-chul Hwang
-
Patent number: 9768062Abstract: A method for forming a low parasitic capacitance contact to a source-drain structure of a fin field effect transistor device. In some embodiments the method includes etching a long trench down to the source-drain structure, the trench being sufficiently long to extend across all the of source-drain regions of the device. A conductive layer is formed on the source-drain structure, and the trench is filled with a first fill material. A second, narrower trench is opened along a portion of the length of the first trench, and filled with a second fill material. The first fill material may be conductive, and may form the contact. If the first fill material is not conductive, a third trench may be opened, in the portion of the first trench not filled with the second fill material, and filled with a conductive material, to form the contact.Type: GrantFiled: September 26, 2016Date of Patent: September 19, 2017Assignee: Samsung Electronics Co., Ltd.Inventors: Jorge A. Kittl, David Seo, Kota Oikawa, Kim Changhwa, Rwik Sengupta, Mark S. Rodder
-
Patent number: 9595610Abstract: A MOSFET may be formed with a strain-inducing mismatch of lattice constants that improves carrier mobility. In exemplary embodiments a MOSFET includes a strain-inducing lattice constant mismatch that is not undermined by a recessing step. In some embodiments a source/drain pattern is grown without a recessing step, thereby avoiding problems associated with a recessing step. Alternatively, a recessing process may be performed in a way that does not expose top surfaces of a strain-relaxed buffer layer. A MOSFET device layer, such as a strain-relaxed buffer layer or a device isolation layer, is unaffected by a recessing step and, as a result, strain may be applied to a channel region without jeopardizing subsequent formation steps.Type: GrantFiled: May 28, 2015Date of Patent: March 14, 2017Assignee: Samsung Electronics Co., Ltd.Inventors: TaeYong Kwon, Shigenobu Maeda, David Seo, Jae-Hwan Lee
-
Patent number: 9525076Abstract: A graphene memory includes a source and a drain spaced apart from each other on a conductive semiconductor substrate, a graphene layer contacting the conductive semiconductor substrate and spaced apart from and between the source and the drain, and a gate electrode on the graphene layer. A Schottky barrier is formed between the conductive semiconductor substrate and the graphene layer such that the graphene layer is used as a charge-trap layer for storing charges.Type: GrantFiled: August 6, 2013Date of Patent: December 20, 2016Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Jae-ho Lee, Hyun-jong Chung, Seong-jun Park, Kyung-eun Byun, David Seo, Hyun-jae Song, Jin-seong Heo
-
Publication number: 20160268418Abstract: Provided are nonvolatile memory transistors and devices including the nonvolatile memory transistors. A nonvolatile memory transistor may include a channel element, a gate electrode corresponding to the channel element, a gate insulation layer between the channel element and the gate electrode, an ionic species moving layer between the gate insulation layer and the gate electrode, and a source and a drain separated from each other with respect to the channel element. A motion of an ionic species at the ionic species moving layer occurs according to a voltage applied to the gate electrode. A threshold voltage changes according to the motion of the ionic species. The nonvolatile memory transistor has a multi-level characteristic.Type: ApplicationFiled: May 26, 2016Publication date: September 15, 2016Inventors: Myoung-jae Lee, Seong-ho Cho, Ho-jung Kim, Young-soo Park, David Seo, In-kyeong Yoo
-
Patent number: 9379319Abstract: Provided are nonvolatile memory transistors and devices including the nonvolatile memory transistors. A nonvolatile memory transistor may include a channel element, a gate electrode corresponding to the channel element, a gate insulation layer between the channel element and the gate electrode, an ionic species moving layer between the gate insulation layer and the gate electrode, and a source and a drain separated from each other with respect to the channel element. A motion of an ionic species at the ionic species moving layer occurs according to a voltage applied to the gate electrode. A threshold voltage changes according to the motion of the ionic species. The nonvolatile memory transistor has a multi-level characteristic.Type: GrantFiled: July 28, 2014Date of Patent: June 28, 2016Assignee: Samsung Electronics Co., Ltd.Inventors: Myoung-jae Lee, Seong-ho Cho, Ho-jung Kim, Young-soo Park, David Seo, In-kyeong Yoo
-
Patent number: 9373685Abstract: A graphene device and an electronic apparatus including the same are provided. According to example embodiments, the graphene device includes a transistor including a source, a gate, and a drain, an active layer through which carriers move, and a graphene layer between the gate and the active layer. The graphene layer may be configured to function both as an electrode of the active layer and a channel layer of the transistor.Type: GrantFiled: February 14, 2014Date of Patent: June 21, 2016Assignee: Samsung Electronics Co., Ltd.Inventors: Hyeon-jin Shin, Kyung-eun Byun, Hyun-jae Song, Seong-jun Park, David Seo, Yun-sung Woo, Dong-wook Lee, Jae-ho Lee, Hyun-jong Chung, Jin-seong Heo, In-kyeong Yoo
-
Publication number: 20160172450Abstract: The present disclosure relates to a semiconductor device including an oxygen gettering layer between a group III-V compound semiconductor layer and a dielectric layer, and a method of fabricating the semiconductor device. The semiconductor device may include a compound semiconductor layer; a dielectric layer disposed on the compound semiconductor layer; and an oxygen gettering layer interposed between the compound semiconductor layer and the dielectric layer. The oxygen gettering layer includes a material having a higher oxygen affinity than a material of the compound semiconductor layer.Type: ApplicationFiled: February 23, 2016Publication date: June 16, 2016Inventors: Dong-soo LEE, Myoung-jae LEE, Seong-ho CHO, Mohammad Rakib UDDIN, David SEO, Moon-seung YANG, Sang-moon LEE, Sung-hun LEE, Ji-hyun HUR, Eui-chul HWANG
-
Patent number: 9359211Abstract: Methods of fabricating graphene using an alloy catalyst may include forming an alloy catalyst layer including nickel on a substrate and forming a graphene layer by supplying hydrocarbon gas onto the alloy catalyst layer. The alloy catalyst layer may include nickel and at least one selected from the group consisting of copper, platinum, iron and gold. When the graphene is fabricated, a catalyst metal that reduces solubility of carbon in Ni may be used together with Ni in the alloy catalyst layer. An amount of carbon that is dissolved may be adjusted and a uniform graphene monolayer may be fabricated.Type: GrantFiled: July 12, 2010Date of Patent: June 7, 2016Assignee: Samsung Electronics Co., Ltd.Inventors: Yun-sung Woo, David Seo, Sun-ae Seo, Hyun-jong Chung, Sae-ra Kang, Jin-seong Heo
-
Patent number: 9306021Abstract: A graphene device includes: a semiconductor substrate having a first region and a second region; a graphene layer on the first region, but not on the second region of the semiconductor substrate; a first electrode on a first portion of the graphene layer; a second electrode on a second portion of the graphene layer; an insulating layer between the graphene layer and the second electrode; and a third electrode on the second region of the semiconductor substrate. The semiconductor substrate has a tunable Schottky barrier formed by junction of the graphene layer and the semiconductor substrate.Type: GrantFiled: April 3, 2014Date of Patent: April 5, 2016Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Hyun-jong Chung, David Seo, Seong-jun Park, Kyung-eun Byun, Hyun-jae Song, Hee-jun Yang, Jin-seong Heo
-
Patent number: 9306008Abstract: The present disclosure relates to a semiconductor device including an oxygen gettering layer between a group III-V compound semiconductor layer and a dielectric layer, and a method of fabricating the semiconductor device. The semiconductor device may include a compound semiconductor layer; a dielectric layer disposed on the compound semiconductor layer; and an oxygen gettering layer interposed between the compound semiconductor layer and the dielectric layer. The oxygen gettering layer includes a material having a higher oxygen affinity than a material of the compound semiconductor layer.Type: GrantFiled: March 13, 2014Date of Patent: April 5, 2016Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Dong-soo Lee, Myoung-Jae Lee, Seong-ho Cho, Mohammad Rakib Uddin, David Seo, Moon-seung Yang, Sang-moon Lee, Sung-hun Lee, Ji-hyun Hur, Eui-chul Hwang
-
Patent number: 9306005Abstract: According to example embodiments, an electronic device includes: a semiconductor layer; a graphene directly contacting a desired (and/or alternatively predetermined) area of the semiconductor layer; and a metal layer on the graphene. The desired (and/or alternatively predetermined) area of the semiconductor layer include one of: a constant doping density, a doping density that is equal to or less than 1019 cm?3, and a depletion width of less than or equal to 3 nm.Type: GrantFiled: December 11, 2013Date of Patent: April 5, 2016Assignee: Samsung Electronics Co., Ltd.Inventors: Kyung-eun Byun, Seong-jun Park, David Seo, Hyun-jae Song, Jae-ho Lee, Hyun-jong Chung, Jin-seong Heo
-
Patent number: 9299789Abstract: A memory device includes a graphene switching device having a source electrode, a drain electrode and a gate electrode. The graphene switching device includes a Schottky barrier formed between the drain electrode and a channel in a direction from the source electrode toward the drain electrode. The memory device need not include additional storage element.Type: GrantFiled: July 16, 2013Date of Patent: March 29, 2016Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: David Seo, Ho-jung Kim, Hyun-jong Chung, Seong-jun Park, Kyung-eun Byun, Hyun-jae Song, Jin-seong Heo
-
Patent number: 9281404Abstract: A switching device includes a semiconductor layer, a graphene layer, a gate insulation layer, and a gate formed in a three-dimensional stacking structure between a first electrode and a second electrode formed on a substrate.Type: GrantFiled: January 3, 2013Date of Patent: March 8, 2016Assignee: Samsung Electronics Co., Ltd.Inventors: Jin-seong Heo, Seong-jun Park, Kyung-eun Byun, David Seo, Hyun-jae Song, Hee-jun Yang, Hyun-jong Chung
-
Publication number: 20160005864Abstract: A MOSFET may be formed with a strain-inducing mismatch of lattice constants that improves carrier mobility. In exemplary embodiments a MOSFET includes a strain-inducing lattice constant mismatch that is not undermined by a recessing step. In some embodiments a source/drain pattern is grown without a recessing step, thereby avoiding problems associated with a recessing step. Alternatively, a recessing process may be performed in a way that does not expose top surfaces of a strain-relaxed buffer layer. A MOSFET device layer, such as a strain-relaxed buffer layer or a device isolation layer, is unaffected by a recessing step and, as a result, strain may be applied to a channel region without jeopardizing subsequent formation steps.Type: ApplicationFiled: May 28, 2015Publication date: January 7, 2016Inventors: TaeYong Kwon, Shigenobu Maeda, David Seo, Jae-Hwan Lee
-
Patent number: 9184236Abstract: A method of transferring graphene includes patterning an upper surface of a substrate to form at least one trench therein, providing a graphene layer on the substrate, the graphene layer including an adhesive liquid thereon, pressing the graphene layer with respect to the substrate, and removing the adhesive liquid by drying the substrate.Type: GrantFiled: August 20, 2012Date of Patent: November 10, 2015Assignee: Samsung Electronics Co., Ltd.Inventors: David Seo, Jin-seong Heo, Hyun-jong Chung, Hee-jun Yang, Seong-jun Park, Hyun-jae Song
-
Patent number: 9166062Abstract: According to example embodiments, a field effect transistor includes a graphene channel layer on a substrate. The graphene channel layer defines a slit. A source electrode and a drain electrode are spaced apart from each other and arranged to apply voltages to the graphene channel layer. A gate insulation layer is between the graphene channel layer and a gate electrode.Type: GrantFiled: April 22, 2015Date of Patent: October 20, 2015Assignees: Samsung Electronics Co., Ltd., Seoul National University R&DB FoundationInventors: Jae-ho Lee, Seong-jun Park, Kyung-eun Byun, David Seo, Hyun-jae Song, Hyung-cheol Shin, Jae-hong Lee, Hyun-jong Chung, Jin-seong Heo
-
Patent number: 9136336Abstract: Inverter logic devices include a gate oxide on a back substrate, a first graphene layer and a second graphene layer separated from each other on the gate oxide, a first electrode layer and a first semiconductor layer separated from each other on the first graphene layer, a second electrode layer and a second semiconductor layer separated from each other on the second graphene layer, and an output electrode on the first and second semiconductor layers and configured to output an output signal. The first semiconductor layer is doped with a different type of impurities selected from n-type impurities and p-type impurities than the second semiconductor layer.Type: GrantFiled: August 24, 2012Date of Patent: September 15, 2015Assignee: Samsung Electronics Co., Ltd.Inventors: Jin-seong Heo, Seong-jun Park, Hyun-jong Chung, Hyun-jae Song, Hee-jun Yang, David Seo