Abstract: An LED chip includes a bond pad suitable for thermosonic or thermocompression bonding such as Sn, AuSn or other metals. The physical dimensions of the bond pad are selected to discourage or prevent solder squeeze-out during thermocompression or thermosonic bonding with or without flux. In some embodiments, an AuSn bond pad is designed to accept 30 g to 70 g of force or more without squeeze-out.

Abstract: A semiconductor light emitting diode includes a semiconductor substrate, an epitaxial layer of n-type Group III nitride on the substrate, a p-type epitaxial layer of Group III nitride on the n-type epitaxial layer and forming a p-n junction with the n-type layer, and a resistive gallium nitride region on the n-type epitaxial layer and adjacent the p-type epitaxial layer for electrically isolating portions of the p-n junction. A metal contact layer is formed on the p-type epitaxial layer. Some embodiments include a semiconductor substrate, an epitaxial layer of n-type Group III nitride on the substrate, a p-type epitaxial layer of Group III nitride on the n-type epitaxial layer and forming a p-n junction with the n-type layer, wherein portions of the epitaxial region are patterned into a mesa and wherein the sidewalls of the mesa comprise a resistive Group III nitride region for electrically isolating portions of the p-n junction.

Abstract: Semiconductor light emitting devices, such as light emitting diodes, include a substrate, an epitaxial region on the substrate that includes a light emitting region such as a light emitting diode region, and a multilayer conductive stack including a reflector layer, on the epitaxial region. A barrier layer is provided on the reflector layer and extending on a sidewall of the reflector layer. The multilayer conductive stack can also include an ohmic layer between the reflector and the epitaxial region. The barrier layer further extends on a sidewall of the ohmic layer. The barrier layer can also extend onto the epitaxial region outside the multilayer conductive stack. The barrier layer can be fabricated as a series of alternating first and second sublayers.

Abstract: A method is disclosed for treating a silicon carbide substrate for improved epitaxial deposition thereon and for use as a precursor in the manufacture of devices such as light emitting diodes. The method includes the steps of implanting dopant atoms of a first conductivity type into the first surface of a conductive silicon carbide wafer having the same conductivity type as the implanting ions at one or more predetermined dopant concentrations and implant energies to form a dopant profile, annealing the implanted wafer, and growing an epitaxial layer on the implanted first surface of the wafer.

Abstract: A method is disclosed for treating a silicon carbide substrate for improved epitaxial deposition thereon and for use as a precursor in the manufacture of devices such as light emitting diodes. The method includes the steps of implanting dopant atoms of a first conductivity type into the first surface of a conductive silicon carbide wafer having the same conductivity type as the implanting ions at one or more predetermined dopant concentrations and implant energies to form a dopant profile, annealing the implanted wafer, and growing an epitaxial layer on the implanted first surface of the wafer.

Abstract: Processing a semiconductor wafer can include forming a plurality of Light Emitting Devices (LED) on a semiconductor wafer having a first thickness. The plurality of LEDs on the wafer are brought into contact with a surface of a carrier to couple the wafer to the carrier. The first thickness of the wafer is reduced to a second thickness that is less than the first thickness by processing the backside of the wafer. The carrier is separated from the plurality of LEDs on the wafer and the wafer is cut to separate the plurality of LEDs from one another. Related devices are also disclosed.

Abstract: Methods of fabricating light emitting diodes and light emitting devices are provided that include a substrate, an n-type epitaxial region on the substrate and a p-type epitaxial region on the n-type epitaxial region. At least a portion of the p-type epitaxial region comprises a mesa with respect to the substrate. An ohmic contact is provided on an exposed portion of the p-type epitaxial layer. The ohmic contact is self aligned to a sidewall of the mesa and to the p-type epitaxial layer such that a sidewall of the ohmic contact is substantially aligned with a sidewall of the mesa and to the p-type epitaxial layer.

Abstract: A semiconductor structure is disclosed that enhances quality control inspection of device. The structure includes a substrate having at least one planar face, a first metal layer on the planar face, and covering some, but not all of the planar face in a first predetermined geometric pattern, and a second metal layer on the planar face, and covering some, but not all of the planar face in a second geometric pattern that is different from the first geometric pattern. A quality control method for manufacturing a semiconductor device is also disclosed. The method includes the steps of placing a first metal layer on a semiconductor face of a device in a first predetermined geometric pattern, placing a second metal layer on the same face of the device as the first layer and in a second predetermined geometric pattern that is different from the first geometric pattern, and then inspecting the device to identify the presence or absence of one or both of the patterns on the face.

Abstract: A contact for a semiconductor device can be formed by forming a metal on a Silicon Carbide (SiC) substrate and annealing an interface location of the metal and the SiC substrate to form a metal-SiC material thereat and avoiding annealing at a location on the SiC substrate to avoid forming the metal-SiC material thereat.

Abstract: The compass system of the present invention utilizes an improved calibration routine in which a processing circuit of the compass recalibrates the compass each time three data points are obtained from a magnetic field sensor that meet predetermined criteria. One such criterion is that the three data points define corners of a triangle that is substantially non-obtuse. When three data points have been obtained that define a triangle meeting this criterion, the processing circuit calculates a center point for a circle upon which all three data points lie by solving the equation x2+y2+Ax+By+C=0 for A, B, and C, using the coordinate values (x,y) for the three data points and defining the center point as (?A/2, ?B/2).

Abstract: A physically robust light emitting diode is disclosed that offers high-reliability in standard packaging and that will withstand high temperature and high humidity conditions. The diode comprises a Group III nitride heterojunction diode with a p-type Group III nitride contact layer, an ohmic contact to the p-type contact layer, and a sputter-deposited silicon nitride composition passivation layer on the ohmic contact. A method of manufacturing a light emitting diode and an LED lamp incorporating the diode are also disclosed.

Abstract: A semiconductor light emitting diode includes a semiconductor substrate, an epitaxial layer of n-type Group III nitride on the substrate, a p-type epitaxial layer of Group III nitride on the n-type epitaxial layer and forming a p-n junction with the n-type layer, and a resistive gallium nitride region on the n-type epitaxial layer and adjacent the p-type epitaxial layer for electrically isolating portions of the p-n junction. A metal contact layer is formed on the p-type epitaxial layer. In method embodiments disclosed, the resistive gallium nitride border is formed by forming an implant mask on the p-type epitaxial region and implanting ions into portions of the p-type epitaxial region to render portions of the p-type epitaxial region semi-insulating. A photoresist mask or a sufficiently thick metal layer may be used as the implant mask.

Abstract: A method is disclosed for treating a silicon carbide substrate for improved epitaxial deposition thereon and for use as a precursor in the manufacture of devices such as light emitting diodes. The method includes the steps of implanting dopant atoms of a first conductivity type into the first surface of a conductive silicon carbide wafer having the same conductivity type as the implanting ions at one or more predetermined dopant concentrations and implant energies to form a dopant profile, annealing the implanted wafer, and growing an epitaxial layer on the implanted first surface of the wafer.

Abstract: Light emitting diodes include a substrate, an epitaxial region on the substrate that includes therein a diode region and a multilayer conductive stack on the epitaxial region opposite the substrate. A passivation layer extends at least partially on the multilayer conductive stack opposite the epitaxial region, to define a bonding region on the multilayer conductive stack opposite the epitaxial region. The passivation layer also extends across the multilayer conductive stack, across the epitaxial region and onto the substrate. The multilayer conductive stack can include an ohmic layer on the epitaxial region opposite the substrate, a reflector layer on the ohmic layer opposite the epitaxial region and a tin barrier layer on the reflector layer opposite the ohmic layer. An adhesion layer also may be provided on the tin barrier layer opposite the reflector layer. A bonding layer also may be provided on the adhesion layer opposite the tin barrier layer.

Abstract: Light emitting device die having a mesa configuration on a substrate and an electrode on the mesa are attached to a submount in a flip-chip configuration by forming predefined pattern of conductive die attach material on at least one of the electrode and the submount and mounting the light emitting device die to the submount. The predefined pattern of conductive die attach material is selected so as to prevent the conductive die attach material from contacting regions of having opposite conductivity types when the light emitting device die is mounted to the submount. The predefined pattern of conductive die attach material may provide a volume of die attach material that is less than a volume defined by an area of the electrode and a distance between the electrode and the submount. Light emitting device dies having predefined patterns of conductive die attach material are also provided.

Abstract: Low voltage logic circuitry is used to permit an entire subsystem of an industrial controller to be placed within a hazardous environment to receive a high speed serial link and undertake the control of multiple control points without expensive and awkward long cable runs and electrically isolating circuits for each cable run. Energy and bandwidth limiting on the high speed link allows power levels commensurate with high data rates yet intrinsic safety of the media allowing it to freely pass in and out of the hazardous area. A mixture of intrinsically safe and non-intrinsically safe equipment on the same logical rack is allowed through a bus isolator providing isolated data communication in backplane fashion between modules while wholly isolating power transmission along the backplane.

Abstract: Low voltage logic circuitry is used to permit an entire subsystem of an industrial controller to be placed within a hazardous environment to receive a high speed serial link and undertake the control of multiple control points without expensive and awkward long cable runs and electrically isolating circuits for each cable run. Energy and bandwidth limiting on the high speed link allows power levels commensurate with high data rates yet intrinsic safety of the media allowing it to freely pass in and out of the hazardous area. A mixture of intrinsically safe and non-intrinsically safe equipment on the same logical rack is allowed through a bus isolator providing isolated data communication in backplane fashion between modules while wholly isolating power transmission along the backplane.

Abstract: Low voltage logic circuitry is used to permit an entire subsystem of an industrial controller to be placed within a hazardous environment to receive a high speed serial link and undertake the control of multiple control points without expensive and awkward long cable runs and electrically isolating circuits for each cable run. Energy and bandwidth limiting on the high speed link allows power levels commensurate with high data rates yet intrinsic safety of the media allowing it to freely pass in and out of the hazardous area. A mixture of intrinsically safe and non-intrinsically safe equipment on the same logical rack is allowed through a bus isolator providing isolated data communication in backplane fashion between modules while wholly isolating power transmission along the backplane.

Abstract: The invention relates in general to the prevention and treatment of microbial infections in transplant patients. More particularly, the invention concerns the use of lymphokines, and specifically gamma interferon (IFN-.gamma.) for the prophylaxis and treatment of microbial infections in transplant recipients, without increasing the incidence of graft rejections.

Abstract: Fluxes for aluminium brazing or welding may be produced by grinding the slag by-product of aluminium boron master alloy production. The grinding is preferably to below 75 microns size but particularly preferably to below 30 microns size. The fluxes may be mixed into water to produce a stable, mobile slurry which may be spray-applied to an aluminium work-piece.