Abstract: A sub-nW voltage reference is presented that provides inherently low process variation and enables trim-free operation for low-dropout regulators and other applications in nW microsystems. Sixty chips from three different wafers in 180 nm CMOS are measured, showing an untrimmed within-wafer ?/? of 0.26% and wafer-to-wafer ?/? of 1.9%. Measurement results also show a temperature coefficient of 48-124 ppm/° C. from ?40° C. to 85° C. Outputting a 0.986V reference voltage, the reference operates down to 1.2V and consumes 114 pW at 25° C.

Abstract: A weighted sum is a key computation for many neural networks and other machine learning algorithms. Integrated circuit designs that perform a weighted sum are presented. Weights are stored as threshold voltages in an array of flash transistors. By putting the circuits into a well-defined voltage state, the transistors that hold one set of weights will pass current equal to the desired sum. The current flowing through a given transistor is unaffected by operation of remaining transistors in the circuit.

Abstract: A self-oscillating DC-DC converter structure is proposed in which an oscillator is completely internalized within the switched-capacitor network. This eliminates power overhead of clock generation and level shifting and enables higher efficiency at lower power levels. Voltage doublers are cascaded to form a complete energy harvester with a wide load range from 5 nW to 5 ?W and self-starting operation down to 140 mV. Because each doubler is self-oscillating, the frequency of each stage can be independently modulated, thereby optimizing the overall conversion efficiency.

Abstract: An environmental sensor implementing a sleep mode timer with an oscillator circuit suitable for low power applications is presented. The oscillator circuit includes a plurality of timer stages cascaded in series with each other. Each timer circuit includes a plurality of transistors and operates to output two voltages with opposite polarities, such that the polarities of the two voltages oscillate periodically based on leakage current in the plurality of transistors. Each timer circuit further includes one or more tuning transistors that operate to adjust a frequency at which the polarities of the voltages oscillate. A complementary-to-absolute temperature (“CTAT”) voltage generator is configured to receive a regulated voltage and supply a bias voltage to the one or more tuning transistors in each of the plurality of timer circuits, where the CTAT voltage generator adjusts the bias voltage linearly and inversely with changes in temperature.

Abstract: A temperature insensitive sub-nA current reference is presented with pA-range power overhead. The main concept is to linearly reduce the gate voltage of a sub-threshold-biased MOSFET as temperature increases, in order to compensate for exponential dependence of drain current on temperature. For example, a MOSFET-only, 20 pA, 780 ppm/° C. current reference that consumes 23 pW is disclosed, marking the lowest reported power among current references. The circuit exploits sub-threshold-biased MOSFETs and a complementary-to-absolute temperature (CTAT) gate voltage to compensate for temperature dependency. The design shows high immunity to supply voltage of 0.58%/V and a load sensitivity of 0.25%/V.

Abstract: A matched filter is provided for signal processing applications such as GNSS and RADAR. The filter includes a plurality of correlator cells configured to receive a digital signal and are arranged so that values of the digital signal can be shifted amongst the plurality of correlator cells. Each correlator cell includes a correlator circuit, a data source and a current source. The correlator circuit is configured to receive a value from the digital signal and operates to correlate the value with a value of the known pattern stored in the data store. The current source is interfaced with the correlator circuit and selectively sources current based on the correlation operation performed by the correlator circuit; and an output circuit is coupled to each of the plurality of correlator cell and operates to generate an output which is correlated to current that is being source collectively by the current sources.

Abstract: An ultra-low power oscillator is designed for wake-up timers that can be used in compact wireless sensors, for example. A constant charge subtraction scheme removes continuous comparator delay from the oscillation period, which is the source of temperature dependence in conventional RC relaxation oscillators. This relaxes comparator design constraints, enabling low power operation. In 0.18 ?m CMOS, the oscillator consumes 5.8 nW at room temperature with temperature stability of 45 ppm/° C. (?10° C. to 90° C.) and 1%/V line sensitivity.

Abstract: A weighted sum is a key computation for many neural networks and other machine learning algorithms. Integrated circuit designs that perform a weighted sum are presented. Weights are stored as threshold voltages in an array of flash transistors. By putting the circuits into a well-defined voltage state, the transistors that hold one set of weights will pass current equal to the desired sum. The current flowing through a given transistor is unaffected by operation of remaining transistors in the circuit.

Abstract: An ultra-low power oscillator is designed for wake-up timers that can be used in compact wireless sensors, for example. A constant charge subtraction scheme removes continuous comparator delay from the oscillation period, which is the source of temperature dependence in conventional RC relaxation oscillators. This relaxes comparator design constraints, enabling low power operation. In 0.18 ?m CMOS, the oscillator consumes 5.8 nW at room temperature with temperature stability of 45 ppm/° C. (?10° C. to 90° C.) and 1%/V line sensitivity.

Abstract: A temperature insensitive sub-nA current reference is presented with pA-range power overhead. The main concept is to linearly reduce the gate voltage of a sub-threshold-biased MOSFET as temperature increases, in order to compensate for exponential dependence of drain current on temperature. For example, a MOSFET-only, 20 pA, 780 ppm/° C. current reference that consumes 23 pW is disclosed, marking the lowest reported power among current references. The circuit exploits sub-threshold-biased MOSFETs and a complementary-to-absolute temperature (CTAT) gate voltage to compensate for temperature dependency. The design shows high immunity to supply voltage of 0.58%/V and a load sensitivity of 0.25%/V.

Abstract: An improved oscillation driver circuit for use in an integrated circuit in combination with an oscillation element. An amplification element is adapted to receive an oscillator output, and to generate an amplified oscillator output. A pulse generator receives the amplified oscillator output and generates positive and negative pulsed outputs substantially in phase with the oscillator output. A driver element is adapted to drive the oscillator input in response to the pulsed outputs.

Abstract: A data processing apparatus is provided for producing a randomized value. A cell in the data processing apparatus comprises a dielectric oxide layer and stress voltage circuitry is configured to apply a stress voltage across the dielectric oxide layer of the cell to cause an oxide breakdown process to occur. Oxide breakdown detection circuitry is configured to determine a current extent of the oxide breakdown process by measuring a response of the dielectric oxide layer to the stress voltage and randomized value determination circuitry is configured to determine a randomized value in dependence on the current extent of the oxide breakdown process.

Abstract: A data processing apparatus is provided for producing a randomized value. A cell in the data processing apparatus comprises a dielectric oxide layer and stress voltage circuitry is configured to apply a stress voltage across the dielectric oxide layer of the cell to cause an oxide breakdown process to occur. Oxide breakdown detection circuitry is configured to determine a current extent of the oxide breakdown process by measuring a response of the dielectric oxide layer to the stress voltage and randomized value determination circuitry is configured to determine a randomized value in dependence on the current extent of the oxide breakdown process.

Abstract: A method of generating valid vertical interconnect positions for a multiple layer integrated circuit including multiple layers stacked vertically above one another and having a bonding interface between at least one pair of layers. The interface is formed by the coupling of a pair of conductive bond patterns formed on facing surfaces of the pair of layers. The method includes defining a candidate transformation origin, defining a sub-region which tessellates across the patterns, applying a predetermined transformation to the patterns at the bonding interface, determining the validity of the candidate transformation origin in dependence on coincidence of at least a subset of the patterns with the transformed patterns, selecting a valid transformation origin, and defining a set of valid vertical interconnect positions associated with the valid transformation origin at positions in the bonding interface where the original and transformed patterns coincided with each other.

Abstract: A data processing apparatus is provided for producing a randomized value. A cell in the data processing apparatus comprises a dielectric oxide layer and stress voltage circuitry is configured to apply a stress voltage across the dielectric oxide layer of the cell to cause an oxide breakdown process to occur. Oxide breakdown detection circuitry is configured to determine a current extent of the oxide breakdown process by measuring a response of the dielectric oxide layer to the stress voltage and randomized value determination circuitry is configured to determine a randomized value in dependence on the current extent of the oxide breakdown process.

Abstract: A memory circuit for use in a data processing circuit is described, in which memory cells have at least two states, each state being determined by both a first voltage level corresponding to a first supply line and a second voltage level corresponding to a second supply line. The memory circuit comprises a readable state in which information stored in a memory cell is readable and an unreadable state in which information stored in said memory cell is reliably retained but unreadable. Changing the first voltage level but keeping the second voltage level substantially constant effects a transition between the readable state and the unreadable state. In use, the static power consumption of the memory cell in the unreadable state is less than static power consumption of the memory cell in the readable state.

Abstract: A memory circuit for use in a data processing circuit is described, in which memory cells have at least two states, each state being determined by both a first voltage level corresponding to a first supply line and a second voltage level corresponding to a second supply line. The memory circuit comprises a readable state in which information stored in a memory cell is readable and an unreadable state in which information stored in said memory cell is reliably retained but unreadable. Changing the first voltage level but keeping the second voltage level substantially constant effects a transition between the readable state and the unreadable state. In use, the static power consumption of the memory cell in the unreadable state is less than static power consumption of the memory cell in the readable state.

Abstract: An integrated circuit includes a plurality of processing stages each including processing logic 1014, a non-delayed signal-capture element 1016, a delayed signal-capture element 1018 and a comparator 1024. The non-delayed signal-capture element 1016 captures an output from the processing logic 1014 at a non-delayed capture time. At a later delayed capture time, the delayed signal-capture element 1018 also captures a value from the processing logic 1014. An error detection circuit 1026 and error correction circuit 1028 detect and correct random errors in the delayed value and supplies an error-checked delayed value to the comparator 1024. The comparator 1024 compares the error-checked delayed value and the non-delayed value and if they are not equal this indicates that the non-delayed value was captured too soon and should be replaced by the error-checked delayed value.

Abstract: A method of improving performance of a dual Vt integrated circuit is disclosed in which a first value is calculated for each transistor of the integrated circuit that has a first threshold voltage level. The first value is based at least in part on delay and leakage of the circuit calculated as if the corresponding transistor had a second threshold voltage level. One transistor is then selected based on the first values. The threshold voltage of the selected transistor is then set to the second threshold voltage level. The area of at least one transistor within the circuit is modified, and the circuit is then sized to a predetermined area. The process may then be repeated if the circuit performance fails to meet a defined constraint.

Abstract: A method for designing and routing circuitry having reduced cross talk. Early noise analysis (22) is performed after global routing (12) but before detailed routing (28) in order to repair problems (24) before detailed routing (28) is performed. In one embodiment, the early noise analysis (22) is preceded by probabilistic extraction (16). In one embodiment, probabilistic extraction (16) includes determining a probability of occurrence for each configuration in a predetermined set of configurations (54). Probabilistic capacitance extraction is then performed (56). A probabilistic distributed coupled RC network is constructed using the extracted capacitances (60). In one embodiment, probabilistic extraction (16) includes estimating aggressor strength (20) using the probabilistic distributed coupled RC network.