Abstract: The present disclosure presents a barrel assembly for a firearm. The barrel assembly includes a barrel having an internal bore and an external surface, and a recoil spring lug affixed to an outside surface of the barrel. The barrel assembly also includes a slide moveably mounted relative to the barrel, and a recoil spring biased on the recoil spring lug and the slide.

Abstract: Various implementations described herein may refer to and may be directed to circuitry for an integrated circuit using topology configurations. For instance, in one implementation, such circuitry may include a memory array having a plurality of memory cells. Such circuitry may also include one or more reconfigurable sense amplifier devices coupled to the memory array and configured to amplify differential voltage levels received from the memory array. The reconfigurable sense amplifier devices may include a plurality of sense amplifier circuits configured to be arranged in one of a plurality of topology configurations, where the topology configurations include a parallel configuration and a cross parallel configuration. The reconfigurable sense amplifier devices may also include one or more switches configured to set the plurality of sense amplifier circuits into the plurality of topological configurations based on one or more control bits.

Abstract: An interconnect within an integrated circuit provides arbitration to select one of a plurality of signal inputs for connection to a signal output. The arbitration applied uses a first arbitration parameter value, in the form of a time stamp value, and, if two or more signal inputs share such a time stamp value, then uses a second arbitration parameter, in the form of a least recently granted value. The time increment applied to the time stamp value associated with each signal input when it is granted access to the signal output is selected to reflect the quality of service to be associated with that signal input. When a comparison is made between time stamp values, the lowest time stamp value is given priority. A large time increment value corresponds to a low priority (quality of service).

Abstract: Physically Unclonable Function (PUF) cells are described, suitable for CMOS technology, where each PUF cell is based upon a two-transistor amplifier design. A PUF cell includes a voltage generator followed by one or more amplifier stages. Also described is a method and apparatus for determining a dark bit mask for an array of PUF cells based on the two-transistor amplifier design.

Abstract: A hammer and a sear for a fire control system includes a safety notch and a spaced apart triggering surface on the hammer and a firing contact surface and a safety contact surface on the sear. The firing contact surface of the sear is precluded from contacting the safety notch of the hammer in both a safety position of the hammer and the sear and a firing position of the hammer and the sear. Further, a normal to the firing contact surface extends through a pivot pin that provides rotation of the sear.

Abstract: The present disclosure presents a barrel assembly for a firearm. The barrel assembly includes a barrel having an internal bore and an external surface, and a recoil spring lug affixed to an outside surface of the barrel. The barrel assembly also includes a slide moveably mounted relative to the barrel, and a recoil spring biased on the recoil spring lug and the slide.

Abstract: Various implementations described herein are directed to an integrated circuit. The integrated circuit may include a charge pump stage having multiple charge storage elements arranged to provide multiple sets of voltages in alternating phases. The integrated circuit may include a voltage multiplexing stage having multiple multiplexers arranged to receive the multiple sets of voltages in the alternating phases. Each multiplexer may provide a selected voltage from the multiple sets of voltages based on a conversion ratio. The integrated circuit may include a voltage summing stage having multiple sampling charge storage elements arranged to receive the selected voltages from each multiplexer and provide an output voltage as a sum of the selected voltages received from each multiplexer.

Abstract: Various implementations described herein are directed to an integrated circuit. The integrated circuit may include a charge pump stage having multiple charge storage elements arranged to provide multiple sets of voltages in alternating phases. The integrated circuit may include a voltage multiplexing stage having multiple multiplexers arranged to receive the multiple sets of voltages in the alternating phases. Each multiplexer may provide a selected voltage from the multiple sets of voltages based on a conversion ratio. The integrated circuit may include a voltage summing stage having multiple sampling charge storage elements arranged to receive the selected voltages from each multiplexer and provide an output voltage as a sum of the selected voltages received from each multiplexer.

Abstract: Various implementations described herein are directed to a device having a charge pump and a capacitor. The charge pump may be configured for coupling between first and second power sources. The capacitor may be configured for coupling between the first power source and an input of the charge pump. In an energy harvest mode, the charge pump may decouple from the first and second power sources, and the first power source may charge the capacitor with a first voltage while the charge pump is decoupled from the first and second power sources. In an energy transfer mode, the charge pump may couple to the capacitor and the second power source to transfer the first voltage from the capacitor to the second power source during discharge of the first voltage from the capacitor.

Abstract: Various implementations described herein are directed to an integrated circuit. The integrated circuit may include a first voltage source providing a first voltage having a first polarity. The integrated circuit may include a second voltage source providing a second voltage having a second polarity that is opposite the first polarity. The integrated circuit may include a first circuit portion configured to receive the first and second voltages and provide one or more feedback voltages. The integrated circuit may include a second circuit portion configured to receive the first and second voltages along with the one or more feedback voltages and provide an output voltage that is proportional to the first voltage based on a rational conversion ratio that is derived by selection of at least one of the first and second voltages and the one or more feedback voltages.

Abstract: The present disclosure presents a gun sight and a method of forming a gun sight. The gun sight includes a sight body, and a diamond affixed to the sight body at a predetermined location to facilitate aiming. The gun sight may further include a mount, wherein the diamond is retained in the mount and the mount is connected or coupled to the sight body.

Abstract: The present disclosure presents a firearm. The firearm includes a frame having a handle and a slide rail guide, the slide rail guide comprising two parallel grooves extending through a long axis of the frame, and a slide having a long axis, the slide comprising two parallel slide rails extending through the long axis of the slide, the two parallel slide rails operable for slidably engaging the two parallel grooves. The firearm also includes a first spacer, the first spacer fixedly attached to one of the frame and the slide, the first spacer operable to slidably engage the slide rails and the slide rail guide providing a first gap between one of the slide rails and the one of the grooves and a second spacer.

Abstract: Various implementations described herein may refer to and may be directed to circuitry for an integrated circuit using topology configurations. For instance, in one implementation, such circuitry may include a memory array having a plurality of memory cells. Such circuitry may also include one or more reconfigurable sense amplifier devices coupled to the memory array and configured to amplify differential voltage levels received from the memory array. The reconfigurable sense amplifier devices may include a plurality of sense amplifier circuits configured to be arranged in one of a plurality of topology configurations, where the topology configurations include a parallel configuration and a cross parallel configuration. The reconfigurable sense amplifier devices may also include one or more switches configured to set the plurality of sense amplifier circuits into the plurality of topological configurations based on one or more control bits.

Abstract: A barrel bushing and retained bias assembly are provided for engaging a barrel of a firearm to accommodate relative longitudinal movement of the barrel bushing and the barrel. The barrel bushing includes a retaining channel for retaining the bias assembly, such that a portion of the bias assembly extends into a bore of the barrel bushing to contact and be partly compressed by the outside diameter of the barrel.

Abstract: A hammer and a sear for a fire control system includes a safety notch and a spaced apart triggering surface on the hammer and a firing contact surface and a safety contact surface on the sear. The firing contact surface of the sear is precluded from contacting the safety notch of the hammer in both a safety position of the hammer and the sear and a firing position of the hammer and the sear. Further, a normal to the firing contact surface extends through a pivot pin that provides rotation of the sear.

Abstract: A measurement circuit and method are provided for measuring a clock node to output node delay of a flip-flop. A main ring oscillator has a plurality of main unit cells arranged in a ring, with each main unit cell comprising a flip-flop and pulse generation circuitry connected to the output node of the flip-flop. The flip-flop is responsive to receipt of an input clock pulse at the clock node to output a data value transition from the output node, and the pulse generation circuitry then generates from the data value transition an input clock pulse for a next main unit cell in the main ring, whereby the main ring oscillator generates a first output signal having a first oscillation period.

Abstract: A protocol for transmitting data from an external device to an electronic device is provided in which the external device transmits a data stream which includes the same data packet repeated multiple times. The data packet has a predetermined length and has a header portion at a predetermined position. A receiver at the electronic device captures a block of data having the predetermined length from the transmitted data stream, and a decoder rotates the captured block of data to place the header portion at the predetermined position within the data packet. This eliminates the need for an accurate jitter-free clock reference at the electronic device. By shifting power consumption and system complexity to the external unit where power is typically not constrained, the energy efficiency of the electronic device can be increased.

Abstract: Systems and methods for electronic devices are presented. A device includes a substrate. An Indium Gallium Nitride (InGaN) nanoring is formed over the substrate. The InGaN nanoring includes an alloy of Indium Nitride (InN) and Gallium Nitride (GaN). The alloy includes at least 6 percent Indium. A GaN layer may be formed over the InGaN nanoring, and a first electrode is formed over the GaN layer. In one embodiment, the alloy includes less than about 70 percent Indium.

Abstract: An interconnect within an integrated circuit provides arbitration to select one of a plurality of signal inputs for connection to a signal output. The arbitration applied uses a first arbitration parameter value, in the form of a time stamp value, and, if two or more signal inputs share such a time stamp value, then uses a second arbitration parameter, in the form of a least recently granted value. The time increment applied to the time stamp value associated with each signal input when it is granted access to the signal output is selected to reflect the quality of service to be associated with that signal input. When a comparison is made between time stamp values, the lowest time stamp value is given priority. A large time increment value corresponds to a low priority (quality of service).