Patents by Inventor David V. Horak
David V. Horak has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10134631Abstract: A size-filtered metal interconnect structure allows formation of metal structures having different compositions. Trenches having different widths are formed in a dielectric material layer. A blocking material layer is conformally deposited to completely fill trenches having a width less than a threshold width. An isotropic etch is performed to remove the blocking material layer in wide trenches, i.e., trenches having a width greater than the threshold width, while narrow trenches, i.e., trenches having a width less than the threshold width, remain plugged with remaining portions of the blocking material layer. The wide trenches are filled and planarized with a first metal to form first metal structures having a width greater than the critical width. The remaining portions of the blocking material layer are removed to form cavities, which are filled with a second metal to form second metal structures having a width less than the critical width.Type: GrantFiled: March 22, 2016Date of Patent: November 20, 2018Assignee: International Business Machines CorporationInventors: David V. Horak, Charles W. Koburger, III, Shom Ponoth, Chih-Chao Yang
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Patent number: 9997367Abstract: A metal layer is deposited over an underlying material layer. The metal layer includes an elemental metal that can be converted into a dielectric metal-containing compound by plasma oxidation and/or nitridation. A hard mask portion is formed over the metal layer. Plasma oxidation or nitridation is performed to convert physically exposed surfaces of the metal layer into the dielectric metal-containing compound. The sequence of a surface pull back of the hard mask portion, trench etching, another surface pull back, and conversion of top surfaces into the dielectric metal-containing compound are repeated to form a line pattern having a spacing that is not limited by lithographic minimum dimensions.Type: GrantFiled: July 18, 2016Date of Patent: June 12, 2018Assignee: International Business Machines CorporationInventors: Chiahsun Tseng, David V. Horak, Chun-chen Yeh, Yunpeng Yin
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Patent number: 9935168Abstract: A method of forming a semiconductor structure includes forming a gate structure having a first conductive material above a semiconductor substrate, gate spacers on opposing sides of the first conductive material, and a first interlevel dielectric (ILD) layer surrounding the gate spacers and the first conductive material. An upper portion of the first conductive material is recessed. The gate spacers are recessed until a height of the gate spacers is less than a height of the gate structure. An isolation liner is deposited above the gate spacers and the first conductive material. A portion of the isolation liner is removed so that a top surface of the first conductive material is exposed. A second conductive material is deposited in a contact hole created above the first conductive material and the gate spacers to form a gate contact.Type: GrantFiled: February 28, 2017Date of Patent: April 3, 2018Assignees: International Business Machines Corporation, GLOBALFOUNDRIES INC.Inventors: David V. Horak, Shom S. Ponoth, Balasubramanian Pranatharthiharan, Ruilong Xie
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Publication number: 20170170266Abstract: A method of forming a semiconductor structure includes forming a gate structure having a first conductive material above a semiconductor substrate, gate spacers on opposing sides of the first conductive material, and a first interlevel dielectric (ILD) layer surrounding the gate spacers and the first conductive material. An upper portion of the first conductive material is recessed. The gate spacers are recessed until a height of the gate spacers is less than a height of the gate structure. An isolation liner is deposited above the gate spacers and the first conductive material. A portion of the isolation liner is removed so that a top surface of the first conductive material is exposed. A second conductive material is deposited in a contact hole created above the first conductive material and the gate spacers to form a gate contact.Type: ApplicationFiled: February 28, 2017Publication date: June 15, 2017Inventors: David V. Horak, Shom S. Ponoth, Balasubramanian Pranatharthiharan, Ruilong Xie
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Patent number: 9660030Abstract: A dielectric disposable gate structure can be formed across a semiconductor material portion, and active semiconductor regions are formed within the semiconductor material portion. Raised active semiconductor regions are grown over the active semiconductor regions while the dielectric disposable gate structure limits the extent of the raised active semiconductor regions. A planarization dielectric layer is formed over the raised active semiconductor regions. In one embodiment, the dielectric disposable gate structure is removed, and a dielectric gate spacer can be formed by conversion of surface portions of the raised active semiconductor regions around a gate cavity. Alternately, an etch mask layer overlying peripheral portions of the disposable gate structure can be formed, and a gate cavity and a dielectric spacer can be formed by anisotropically etching an unmasked portion of the dielectric disposable gate structure. A replacement gate structure can be formed in the gate cavity.Type: GrantFiled: August 29, 2014Date of Patent: May 23, 2017Assignee: GLOBALFOUNDRIES INC.Inventors: Shom Ponoth, Marc A. Bergendahl, Steven J. Holmes, David V. Horak, Charles W. Koburger, III, Chih-Chao Yang
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Patent number: 9620619Abstract: A borderless contact structure or partially borderless contact structure and methods of manufacture are disclosed. The method includes forming a gate structure and a space within the gate structure, defined by spacers. The method further includes blanket depositing a sealing material in the space, over the gate structure and on a semiconductor material. The method further includes removing the sealing material from over the gate structure and on the semiconductor material, leaving the sealing material within the space. The method further includes forming an interlevel dielectric material over the gate structure. The method further includes patterning the interlevel dielectric material to form an opening exposing the semiconductor material and a portion of the gate structure. The method further includes forming a contact in the opening formed in the interlevel dielectric material.Type: GrantFiled: January 12, 2012Date of Patent: April 11, 2017Assignee: GLOBALFOUNDRIES INC.Inventors: Veeraraghavan S. Basker, David V. Horak, Charles W. Koburger, III, Shom Ponoth, Chih-Chao Yang
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Patent number: 9614047Abstract: A method of forming a semiconductor structure includes forming a gate structure having a first conductive material above a semiconductor substrate, gate spacers on opposing sides of the first conductive material, and a first interlevel dielectric (ILD) layer surrounding the gate spacers and the first conductive material. An upper portion of the first conductive material is recessed. The gate spacers are recessed until a height of the gate spacers is less than a height of the gate structure. An isolation liner is deposited above the gate spacers and the first conductive material. A portion of the isolation liner is removed so that a top surface of the first conductive material is exposed. A second conductive material is deposited in a contact hole created above the first conductive material and the gate spacers to form a gate contact.Type: GrantFiled: May 12, 2016Date of Patent: April 4, 2017Assignees: International Business Machines Corporation, GlobalFoundries, Inc.Inventors: David V. Horak, Shom S. Ponoth, Balasubramanian Pranatharthiharan, Ruilong Xie
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Patent number: 9515070Abstract: A semiconductor structure which includes: a fin on a semiconductor substrate; and a gate structure wrapped around the fin. The gate structure includes: spaced apart spacers to form an opening, the spacers being perpendicular to the fin, the spacers having a height with respect to the fin; a high-k dielectric material in the opening and over the fin, the high-k dielectric material in contact with the spacers and a bottom of the opening; a work function metal in contact with the high-k dielectric material that is over the fin, the spacers and the bottom of the opening, the work function metal that is in contact with the high-k dielectric material having a height in the opening that is less than the height of the spacers, the high-k dielectric material and the work function metal only partially filling the opening; and a metal completely filling the opening.Type: GrantFiled: December 2, 2015Date of Patent: December 6, 2016Assignee: International Business Machines CorporationInventors: David V. Horak, Effendi Leobandung, Stefan Schmitz, Junli Wang
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Publication number: 20160329214Abstract: A metal layer is deposited over an underlying material layer. The metal layer includes an elemental metal that can be converted into a dielectric metal-containing compound by plasma oxidation and/or nitridation. A hard mask portion is formed over the metal layer. Plasma oxidation or nitridation is performed to convert physically exposed surfaces of the metal layer into the dielectric metal-containing compound. The sequence of a surface pull back of the hard mask portion, trench etching, another surface pull back, and conversion of top surfaces into the dielectric metal-containing compound are repeated to form a line pattern having a spacing that is not limited by lithographic minimum dimensions.Type: ApplicationFiled: July 18, 2016Publication date: November 10, 2016Inventors: Chiahsun Tseng, David V. Horak, Chun-chen Yeh, Yunpeng Yin
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Patent number: 9484254Abstract: A size-filtered metal interconnect structure allows formation of metal structures having different compositions. Trenches having different widths are formed in a dielectric material layer. A blocking material layer is conformally deposited to completely fill trenches having a width less than a threshold width. An isotropic etch is performed to remove the blocking material layer in wide trenches, i.e., trenches having a width greater than the threshold width, while narrow trenches, i.e., trenches having a width less than the threshold width, remain plugged with remaining portions of the blocking material layer. The wide trenches are filled and planarized with a first metal to form first metal structures having a width greater than the critical width. The remaining portions of the blocking material layer are removed to form cavities, which are filled with a second metal to form second metal structures having a width less than the critical width.Type: GrantFiled: November 1, 2013Date of Patent: November 1, 2016Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: David V. Horak, Charles W. Koburger, III, Shom Ponoth, Chih-Chao Yang
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Publication number: 20160260812Abstract: A method of forming a semiconductor structure includes forming a gate structure having a first conductive material above a semiconductor substrate, gate spacers on opposing sides of the first conductive material, and a first interlevel dielectric (ILD) layer surrounding the gate spacers and the first conductive material. An upper portion of the first conductive material is recessed. The gate spacers are recessed until a height of the gate spacers is less than a height of the gate structure. An isolation liner is deposited above the gate spacers and the first conductive material. A portion of the isolation liner is removed so that a top surface of the first conductive material is exposed. A second conductive material is deposited in a contact hole created above the first conductive material and the gate spacers to form a gate contact.Type: ApplicationFiled: May 12, 2016Publication date: September 8, 2016Inventors: David V. Horak, Shom S. Ponoth, Balasubramanian Pranatharthiharan, Ruilong Xie
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Patent number: 9396957Abstract: A metal layer is deposited over an underlying material layer. The metal layer includes an elemental metal that can be converted into a dielectric metal-containing compound by plasma oxidation and/or nitridation. A hard mask portion is formed over the metal layer. Plasma oxidation or nitridation is performed to convert physically exposed surfaces of the metal layer into the dielectric metal-containing compound. The sequence of a surface pull back of the hard mask portion, trench etching, another surface pull back, and conversion of top surfaces into the dielectric metal-containing compound are repeated to form a line pattern having a spacing that is not limited by lithographic minimum dimensions.Type: GrantFiled: August 11, 2014Date of Patent: July 19, 2016Assignee: International Business Machines CorporationInventors: Chiahsun Tseng, David V. Horak, Chun-chen Yeh, Yunpeng Yin
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Publication number: 20160204064Abstract: A size-filtered metal interconnect structure allows formation of metal structures having different compositions. Trenches having different widths are formed in a dielectric material layer. A blocking material layer is conformally deposited to completely fill trenches having a width less than a threshold width. An isotropic etch is performed to remove the blocking material layer in wide trenches, i.e., trenches having a width greater than the threshold width, while narrow trenches, i.e., trenches having a width less than the threshold width, remain plugged with remaining portions of the blocking material layer. The wide trenches are filled and planarized with a first metal to form first metal structures having a width greater than the critical width. The remaining portions of the blocking material layer are removed to form cavities, which are filled with a second metal to form second metal structures having a width less than the critical width.Type: ApplicationFiled: March 22, 2016Publication date: July 14, 2016Inventors: David V. Horak, Charles W. Koburger, III, Shom Ponoth, Chih-Chao Yang
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Patent number: 9379198Abstract: An integrated circuit structure with a selectively formed and at least partially oxidized metal cap over a gate. In one embodiment, an integrated circuit structure has: a substrate; a metal gate located over the substrate; at least one liner layer over the substrate and substantially surrounding the metal gate; and an at least partially oxidized etch stop layer located directly over the metal gate, the etch stop layer including at least one of cobalt (Co), manganese (Mn), tungsten (W), iridium (Ir), rhodium (Rh) or ruthenium (Ru).Type: GrantFiled: September 24, 2014Date of Patent: June 28, 2016Assignee: GLOBALFOUNDRIES INC.Inventors: Chih-Chao Yang, David V. Horak, Charles W. Koburger, Shom Ponoth
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Patent number: 9373580Abstract: A first metallic hard mask layer over an interconnect-level dielectric layer is patterned with a line pattern. At least one dielectric material layer, a second metallic hard mask layer, a first organic planarization layer (OPL), and a first photoresist are applied above the first metallic hard mask layer. A first via pattern is transferred from the first photoresist layer into the second metallic hard mask layer. A second OPL and a second photoresist are applied and patterned with a second via pattern, which is transferred into the second metallic hard mask layer. A first composite pattern of the first and second via patterns is transferred into the at least one dielectric material layer. A second composite pattern that limits the first composite pattern with the areas of the openings in the first metallic hard mask layer is transferred into the interconnect-level dielectric layer.Type: GrantFiled: December 24, 2013Date of Patent: June 21, 2016Assignee: GLOBALFOUNDRIES INC.Inventors: John C. Arnold, Sean D. Burns, Steven J. Holmes, David V. Horak, Muthumanickam Sankarapandian, Yunpeng Yin
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Patent number: 9368590Abstract: A method is provided for fabricating an integrated circuit that includes multiple transistors. A replacement gate stack is formed on a semiconductor layer, a gate spacer is formed, and a dielectric layer is formed. The dummy gate stack is removed to form a cavity. A gate dielectric and a work function metal layer are formed in the cavity. The cavity is filled with a gate conductor. One and only one of the gate conductor and the work function metal layer are selectively recessed. An oxide film is formed in the recess such that its upper surface is co-planar with the upper surface of the dielectric layer. The oxide film is used to selectively grow an oxide cap. An interlayer dielectric is formed and etched to form a cavity for a source/drain contact. A source/drain contact is formed in the contact cavity, with a portion of the source/drain contact being located directly on the oxide cap.Type: GrantFiled: November 6, 2013Date of Patent: June 14, 2016Assignee: GLOBALFOUNDRIES INC.Inventors: Susan S. Fan, Balasubramanian S. Haran, David V. Horak, Charles W. Koburger
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Patent number: 9349598Abstract: A method of forming a semiconductor structure includes forming a gate structure having a first conductive material above a semiconductor substrate, gate spacers on opposing sides of the first conductive material, and a first interlevel dielectric (ILD) layer surrounding the gate spacers and the first conductive material. An upper portion of the first conductive material is recessed. The gate spacers are recessed until a height of the gate spacers is less than a height of the gate structure. An isolation liner is deposited above the gate spacers and the first conductive material. A portion of the isolation liner is removed so that a top surface of the first conductive material is exposed. A second conductive material is deposited in a contact hole created above the first conductive material and the gate spacers to form a gate contact.Type: GrantFiled: August 21, 2015Date of Patent: May 24, 2016Assignees: INTERNATIONAL BUSINESS MACHINES CORPORATION, GLOBALFOUNDRIES INC.Inventors: David V. Horak, Shom S. Ponoth, Balasubramanian Pranatharthiharan, Ruilong Xie
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Patent number: 9332628Abstract: A microelectronic structure and a method for fabricating the microelectronic structure provide a plurality of voids interposed between a plurality of conductor layers. The plurality of voids is also located between a liner layer and an inter-level dielectric layer. The voids provide for enhanced electrical performance of the microelectronic structure.Type: GrantFiled: June 15, 2015Date of Patent: May 3, 2016Assignee: GLOBALFOUNDRIES INC.Inventors: Daniel C. Edelstein, David V. Horak, Elbert E. Huang, Satyanarayana V. Nitta, Takeshi Nogami, Shom Ponoth, Terry A. Spooner
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Patent number: 9330962Abstract: A metal layer is deposited over a material layer. The metal layer includes an elemental metal that can be converted into a dielectric metal-containing compound by plasma oxidation or nitridation. A hard mask portion is formed over the metal layer. A plasma impermeable spacer is formed on at least one first sidewall of the hard mask portion, while at least one second sidewall of the hard mask portion is physically exposed. Plasma oxidation or nitridation is performed to convert physically exposed surfaces of the metal layer into the dielectric metal-containing compound. A sequence of a surface pull back of the hard mask portion, cavity etching, another surface pull back, and conversion of top surfaces into the dielectric metal-containing compound are repeated to form a hole pattern having a spacing that is not limited by lithographic minimum dimensions.Type: GrantFiled: August 12, 2014Date of Patent: May 3, 2016Assignee: International Business Machines CorporationInventors: Chiahsun Tseng, David V. Horak, Chun-chen Yeh, Yunpeng Yin
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Publication number: 20160086944Abstract: A semiconductor structure which includes: a fin on a semiconductor substrate; and a gate structure wrapped around the fin. The gate structure includes: spaced apart spacers to form an opening, the spacers being perpendicular to the fin, the spacers having a height with respect to the fin; a high-k dielectric material in the opening and over the fin, the high-k dielectric material in contact with the spacers and a bottom of the opening; a work function metal in contact with the high-k dielectric material that is over the fin, the spacers and the bottom of the opening, the work function metal that is in contact with the high-k dielectric material having a height in the opening that is less than the height of the spacers, the high-k dielectric material and the work function metal only partially filling the opening; and a metal completely filling the opening.Type: ApplicationFiled: December 2, 2015Publication date: March 24, 2016Inventors: David V. Horak, Effendi Leobandung, Stefan Schmitz, Junli Wang