Patents by Inventor David V. Horak
David V. Horak has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9269611Abstract: Integrated circuits and methods of forming integrated circuits are provided. An integrated circuit includes a gate electrode structure overlying a base substrate. The gate electrode structure includes a gate electrode, with a cap disposed over the gate electrode and sidewall spacers disposed adjacent to sidewalls of the gate electrode structure. A source and drain region are formed in the base substrate aligned with the gate electrode structure. A first dielectric layer is disposed adjacent to the sidewall spacers. The sidewall spacers and the cap have recessed surfaces below a top surface of the first dielectric layer, and a protecting layer is disposed over the recessed surfaces. A second dielectric layer is disposed over the first dielectric layer and the protecting layer. Electrical interconnects are disposed through the first dielectric layer and the second dielectric layer, and the electrical interconnects are in electrical communication with the respective source and drain regions.Type: GrantFiled: January 21, 2014Date of Patent: February 23, 2016Assignees: GLOBALFOUNDRIES, INC., INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Daniel Thanh Khae Pham, Xiuyu Cai, Bala Subramanian Pranatharthi Haran, Charan Veera Venkata Satya Surisetty, Jin Wook Lee, Shom Ponoth, David V. Horak
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Patent number: 9269621Abstract: A stack of a first metal line and a first dielectric cap material portion is formed within a line trench of first dielectric material layer. A second dielectric material layer is formed thereafter. A line trench extending between the top surface and the bottom surface of the second dielectric material layer is patterned. A photoresist layer is applied over the second dielectric material layer and patterned with a via pattern. An underlying portion of the first dielectric cap material is removed by an etch selective to the dielectric materials of the first and second dielectric material layer to form a via cavity that is laterally confined along the widthwise direction of the line trench and along the widthwise direction of the first metal line. A dual damascene line and via structure is formed, which includes a via structure that is laterally confined along two independent horizontal directions.Type: GrantFiled: August 1, 2014Date of Patent: February 23, 2016Assignee: GLOBALFOUNDRIES INC.Inventors: Steven J. Holmes, David V. Horak, Charles W. Koburger, III, Shom Ponoth, Chih-Chao Yang
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Patent number: 9263290Abstract: Fin structures and methods of manufacturing fin structures using a dual-material sidewall image transfer mask to enable patterning of sub-lithographic features is disclosed. The method of forming a plurality of fins includes forming a first set of fins having a first pitch. The method further includes forming an adjacent fin to the first set of fins. The adjacent fin and a nearest fin of the first set of fins have a second pitch larger than the first pitch. The first set of fins and the adjacent fin are sub-lithographic features formed using a sidewall image transfer process.Type: GrantFiled: September 2, 2015Date of Patent: February 16, 2016Assignee: GLOBALFOUNDRIES INC.Inventors: Marc A. Bergendahl, David V. Horak, Charles W. Koburger, III, Shom Ponoth, Chih-Chao Yang
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Patent number: 9263388Abstract: A method is provided that includes first etching a substrate according to a first mask. The first etching forms a first etch feature in the substrate to a first depth. The first etching also forms a sliver opening in the substrate. The sliver opening may then be filled with a fill material. A second mask may be formed by removing a portion of the first mask. The substrate exposed by the second mask may be etched with a second etch, in which the second etching is selective to the fill material. The second etching extends the first etch feature to a second depth that is greater than the first depth, and the second etch forms a second etch feature. The first etch feature and the second etch feature may then be filled with a conductive metal.Type: GrantFiled: April 16, 2015Date of Patent: February 16, 2016Assignee: GLOBALFOUNDRIES INC.Inventors: Steven J. Holmes, David V. Horak, Charles W. Koburger, III, Shom Ponoth, Chih-Chao Yang
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Patent number: 9231080Abstract: A replacement metal gate process which includes forming a fin on a semiconductor substrate; forming a dummy gate structure on the fin; removing the dummy gate structure to leave an opening that is to be filled with a permanent gate structure; depositing a high dielectric constant (high-k) dielectric material in the opening and over the fin; depositing a work function metal in the opening and over the fin so as to be in contact with the high-k dielectric material, the high k dielectric material and the work function metal only partially filling the opening; filling a remainder of the opening with an organic material; etching the organic material until it is partially removed from the opening; etching the work function metal until it is at a same level as the organic material; removing the organic material; and filling the opening with a metal until the opening is completely filled.Type: GrantFiled: March 24, 2014Date of Patent: January 5, 2016Assignee: International Business Machines CorporationInventors: David V. Horak, Effendi Leobandung, Stefan Schmitz, Junli Wang
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Publication number: 20150380262Abstract: Fin structures and methods of manufacturing fin structures using a dual-material sidewall image transfer mask to enable patterning of sub-lithographic features is disclosed. The method of forming a plurality of fins includes forming a first set of fins having a first pitch. The method further includes forming an adjacent fin to the first set of fins. The adjacent fin and a nearest fin of the first set of fins have a second pitch larger than the first pitch. The first set of fins and the adjacent fin are sub-lithographic features formed using a sidewall image transfer process.Type: ApplicationFiled: September 2, 2015Publication date: December 31, 2015Inventors: Marc A. Bergendahl, David V. Horak, Charles W. Koburger, III, Shom Ponoth, Chih-Chao Yang
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Publication number: 20150357409Abstract: A method of forming a semiconductor structure includes forming a gate structure having a first conductive material above a semiconductor substrate, gate spacers on opposing sides of the first conductive material, and a first interlevel dielectric (ILD) layer surrounding the gate spacers and the first conductive material. An upper portion of the first conductive material is recessed. The gate spacers are recessed until a height of the gate spacers is less than a height of the gate structure. An isolation liner is deposited above the gate spacers and the first conductive material. A portion of the isolation liner is removed so that a top surface of the first conductive material is exposed. A second conductive material is deposited in a contact hole created above the first conductive material and the gate spacers to form a gate contact.Type: ApplicationFiled: August 21, 2015Publication date: December 10, 2015Inventors: David V. Horak, Shom S. Ponoth, Balasubramanian Pranatharthiharan, Ruilong Xie
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Patent number: 9202879Abstract: In a replacement gate scheme, after formation of a gate dielectric layer, a work function material layer completely fills a narrow gate trench, while not filling a wide gate trench. A dielectric material layer is deposited and planarized over the work function material layer, and is subsequently recessed to form a dielectric material portion overlying a horizontal portion of the work function material layer within the wide gate trench. The work function material layer is recessed employing the dielectric material portion as a part of an etch mask to form work function material portions. A conductive material is deposited and planarized to form gate conductor portions, and a dielectric material is deposited and planarized to form gate cap dielectrics.Type: GrantFiled: February 25, 2013Date of Patent: December 1, 2015Assignee: GLOBALFOUNDRIES INC.Inventors: Charles W. Koburger, III, Marc A. Bergendahl, David V. Horak, Shom Ponoth, Chih-Chao Yang
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Publication number: 20150340462Abstract: A approach for recessing and capping metal gate structures is disclosed. Embodiments include: forming a dummy gate electrode on a substrate; forming a hard mask over the dummy gate electrode; forming spacers on opposite sides of the dummy gate electrode and the hard mask; forming an interlayer dielectric (ILD) over the substrate adjacent the spacers; forming a first trench in the ILD down to the dummy gate electrode; removing the dummy gate electrode to form a second trench below the first trench; forming a metal gate structure in the first and second trenches; and forming a gate cap over the metal gate structure.Type: ApplicationFiled: July 30, 2015Publication date: November 26, 2015Inventors: Ruilong XIE, David V. HORAK, Su Chen FAN, Pranatharthiharan Haran BALASUBRAMANIAN
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Patent number: 9177820Abstract: Fin structures and methods of manufacturing fin structures using a dual-material sidewall image transfer mask to enable patterning of sub-lithographic features is disclosed. The method of forming a plurality of fins includes forming a first set of fins having a first pitch. The method further includes forming an adjacent fin to the first set of fins. The adjacent fin and a nearest fin of the first set of fins have a second pitch larger than the first pitch. The first set of fins and the adjacent fin are sub-lithographic features formed using a sidewall image transfer process.Type: GrantFiled: October 24, 2012Date of Patent: November 3, 2015Assignee: GLOBALFOUNDRIES U.S. 2 LLCInventors: Marc A. Bergendahl, David V. Horak, Charles W. Koburger, III, Shom Ponoth, Chih-Chao Yang
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Patent number: 9159653Abstract: A structure and method of making the structure. The structure includes a dielectric layer on a substrate; a first wire formed in a first trench in the dielectric layer, a first liner on sidewalls and a bottom of the first trench and a first copper layer filling all remaining space in the first trench; a second wire formed in a second trench in the dielectric layer, a second liner on sidewalls and a bottom of the second trench and a second copper layer filling all remaining space in the second trench; and an electromigration stop formed in a third trench in the dielectric layer, a third liner on sidewalls and a bottom of the third trench and a third copper layer filling all remaining space in the third trench, the electromigration stop between and abutting respective ends of the first and second wires.Type: GrantFiled: June 2, 2014Date of Patent: October 13, 2015Assignee: GLOBALFOUNDRIES INC.Inventors: Chih-Chao Yang, Marc A. Bergendahl, David V. Horak, Baozhen Li, Shom Ponoth
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Publication number: 20150289361Abstract: A microelectronic structure and a method for fabricating the microelectronic structure provide a plurality of voids interposed between a plurality of conductor layers. The plurality of voids is also located between a liner layer and an inter-level dielectric layer. The voids provide for enhanced electrical performance of the microelectronic structure.Type: ApplicationFiled: June 15, 2015Publication date: October 8, 2015Inventors: Daniel C. Edelstein, David V. Horak, Elbert E. Huang, Satyanarayana V. Nitta, Takeshi Nogami, Shom Ponoth, Terry A. Spooner
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Patent number: 9147576Abstract: A method of forming a semiconductor structure includes forming a gate structure having a first conductive material above a semiconductor substrate, gate spacers on opposing sides of the first conductive material, and a first interlevel dielectric (ILD) layer surrounding the gate spacers and the first conductive material. An upper portion of the first conductive material is recessed. The gate spacers are recessed until a height of the gate spacers is less than a height of the gate structure. An isolation liner is deposited above the gate spacers and the first conductive material. A portion of the isolation liner is removed so that a top surface of the first conductive material is exposed. A second conductive material is deposited in a contact hole created above the first conductive material and the gate spacers to form a gate contact.Type: GrantFiled: January 23, 2014Date of Patent: September 29, 2015Assignees: International Business Machines Corporation, Globalfoundries, Inc.Inventors: David V. Horak, Shom S. Ponoth, Balasubramanian Pranatharthiharan, Ruilong Xie
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Publication number: 20150270373Abstract: A replacement metal gate process which includes forming a fin on a semiconductor substrate; forming a dummy gate structure on the fin; removing the dummy gate structure to leave an opening that is to be filled with a permanent gate structure; depositing a high dielectric constant (high-k) dielectric material in the opening and over the fin; depositing a work function metal in the opening and over the fin so as to be in contact with the high-k dielectric material, the high k dielectric material and the work function metal only partially filling the opening; filling a remainder of the opening with an organic material; etching the organic material until it is partially removed from the opening; etching the work function metal until it is at a same level as the organic material; removing the organic material; and filling the opening with a metal until the opening is completely filled.Type: ApplicationFiled: March 24, 2014Publication date: September 24, 2015Applicant: Intemational Business Machines CorporationInventors: David V. Horak, Effendi Leobandung, Stefan Schmitz, Junli Wang
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Patent number: 9141749Abstract: A method of forming a semiconductor structure includes forming a sacrificial conductive material layer. The method also includes forming a trench in the sacrificial conductive material layer. The method further includes forming a conductive feature in the trench. The method additionally includes removing the sacrificial conductive material layer selective to the conductive feature. The method also includes forming an insulating layer around the conductive feature to embed the conductive feature in the insulating layer.Type: GrantFiled: November 1, 2013Date of Patent: September 22, 2015Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: David V. Horak, Charles W. Koburger, III, Shom Ponoth, Chih-Chao Yang
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Patent number: 9130029Abstract: A approach for recessing and capping metal gate structures is disclosed. Embodiments include: forming a dummy gate electrode on a substrate; forming a hard mask over the dummy gate electrode; forming spacers on opposite sides of the dummy gate electrode and the hard mask; forming an interlayer dielectric (ILD) over the substrate adjacent the spacers; forming a first trench in the ILD down to the dummy gate electrode; removing the dummy gate electrode to form a second trench below the first trench; forming a metal gate structure in the first and second trenches; and forming a gate cap over the metal gate structure.Type: GrantFiled: February 14, 2014Date of Patent: September 8, 2015Assignee: GLOBALFOUNDRIES Singapore Pte. Ltd.Inventors: Ruilong Xie, David V. Horak, Su Chen Fan, Pranatharthiharan Haran Balasubramanian
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Patent number: 9105641Abstract: The profile of a via can be controlled by forming a profile control liner within each via opening that is formed into a dielectric material prior to forming a line opening within the dielectric material. The presence of the profile control liner within each via opening during the formation of the line opening prevents rounding of the corners of a dielectric material portion that is present beneath the line opening and adjacent the via opening.Type: GrantFiled: September 15, 2014Date of Patent: August 11, 2015Assignee: International Business Machines CorporationInventors: Shyng-Tsong Chen, Samuel S. Choi, Steven J. Holmes, David V. Horak, Charles W. Koburger, III, Wai-Kin Li, Christopher J. Penny, Shom Ponoth, Chih-Chao Yang, Yunpeng Yin
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Patent number: 9105693Abstract: A microelectronic structure and a method for fabricating the microelectronic structure provide a plurality of voids interposed between a plurality of conductor layers. The plurality of voids is also located between a liner layer and an inter-level dielectric layer. The voids provide for enhanced electrical performance of the microelectronic structure.Type: GrantFiled: September 13, 2012Date of Patent: August 11, 2015Assignee: International Business Machines CorporationInventors: Daniel C. Edelstein, David V. Horak, Elbert E. Huang, Satyanarayana V. Nitta, Takeshi Nogami, Shom Ponoth, Terry A. Spooner
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Publication number: 20150221591Abstract: A method is provided that includes first etching a substrate according to a first mask. The first etching forms a first etch feature in the substrate to a first depth. The first etching also forms a sliver opening in the substrate. The sliver opening may then be filled with a fill material. A second mask may be formed by removing a portion of the first mask. The substrate exposed by the second mask may be etched with a second etch, in which the second etching is selective to the fill material. The second etching extends the first etch feature to a second depth that is greater than the first depth, and the second etch forms a second etch feature. The first etch feature and the second etch feature may then be filled with a conductive metal.Type: ApplicationFiled: April 16, 2015Publication date: August 6, 2015Inventors: Steven J. Holmes, David V. Horak, Charles W. Koburger, III, Shom Ponoth, Chih-Chao Yang
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Publication number: 20150206844Abstract: Integrated circuits and methods of forming integrated circuits are provided. An integrated circuit includes a gate electrode structure overlying a base substrate. The gate electrode structure includes a gate electrode, with a cap disposed over the gate electrode and sidewall spacers disposed adjacent to sidewalls of the gate electrode structure. A source and drain region are formed in the base substrate aligned with the gate electrode structure. A first dielectric layer is disposed adjacent to the sidewall spacers. The sidewall spacers and the cap have recessed surfaces below a top surface of the first dielectric layer, and a protecting layer is disposed over the recessed surfaces. A second dielectric layer is disposed over the first dielectric layer and the protecting layer. Electrical interconnects are disposed through the first dielectric layer and the second dielectric layer, and the electrical interconnects are in electrical communication with the respective source and drain regions.Type: ApplicationFiled: January 21, 2014Publication date: July 23, 2015Applicants: International Business Machines Corporation, Globalfoundries, Inc.Inventors: Daniel Thanh Khae Pham, Xiuyu Cai, Bala Subramanian Pranatharthi Haran, Charan Veera Venkata Satya Surisetty, Jin Wook Lee, Shom Ponoth, David V. Horak