Abstract: A data processing system incorporating an arithmetic logic unit 20, 22, 24 having an N-bit data pathway and supporting parallel operation program instruction words in which to independent arithmetic operations are carried out in parallel by the arithmetic logic unit upon (N/2)-bit input operand words. Two sets of condition code flags N, Z, C V, SN, SZ, SC, SV responsive to the separate arithmetic logic operations are provided.

Abstract: A data processing system is described utilising two instruction sets. Both instruction sets control processing using full N-bit data pathways within a processor core 2. One instruction set is a 32-bit instruction set and the other is a 16-bit instruction set. Both instruction sets are permanently installed and have associated instruction decoding hardware 30, 36, 38.

Abstract: A data processing system employing registers for holding data to be processed is described. The registers are grouped into sets of registers 2. A register selecting instruction word controls selection of a particular ones of the registers from within the sets of registers 2 to be available for data processing. The register selecting instruction word includes control fields for each set of registers, the bits of each control field specifying a register swap within the a respective set of register. The new register to be selected is derived from an exclusive OR operation performed upon a currently selected register identification word and the control field for that set of registers.

Abstract: A CPU architecture is provided having a user mode (User32), a plurality of exception modes (IRQ32 etc) and a system mode (System) entered via one of the exception modes. The system mode re-uses the same set of registers (16) as the user mode and yet has access to a set of privileged resources compared to the standard resources of the user mode. Interrupt of the same type are disabled when the system is already in that exception mode, but are re-enabled when the system is moved into the system mode. Branch instructions may be used in the user and system modes, but not the exception modes.

Abstract: A data processing apparatus and method are described in which a reset function for recovering from a system crash is provided. Upon activation of a reset signal (nRESET), the contents of a program counter (R15pc) are saved within another register (R14svc) prior to the reinitialization of the system. The contents of the register saving the program counter value are preserved through the reset operation to provide information to a person seeking to debug the system as to where a particular problem requiring the reset signal to be initiated occurred within the instruction address sequence.