Abstract: A method for adjusting a qubit includes measuring a qubit characteristic of a qubit device and computing a modification to correct the qubit characteristic. A geometry of a shunt capacitor is adjusted using a laser direct write process. The qubit characteristic is verified.

Abstract: A technique relates to a device. First thin films are characterized by having a first opposing surface and a first connection surface in which the first connection surface is in physical contact with a first superconducting region. Second thin films are characterized by having a second opposing surface and a second connection surface in which the first and second opposing surfaces are opposite one another. The second connection surface is in physical contact with a second superconducting region. A solder material electrically connects the first and second opposing surfaces, and the solder material is characterized by maintaining a low ohmic electrical contact between the first and second opposing surfaces at temperatures below 100 degrees Kelvin. The first and second superconducting regions are formed of materials that have a melting point of at least 700 degrees Celsius.

Abstract: A technique relates to a structure. An under-bump-metallization (UBM) structure includes a first region and a second region. The first and second regions are laterally positioned in the UBM structure. The first region includes a superconducting material. A substrate opposes the UBM structure. A superconducting solder material joins the first region to the substrate and the second region to the substrate.

Abstract: A technique relates to a superconducting qubit. A Josephson junction includes a first superconductor and a second superconductor formed on a non-superconducting metal. A capacitor is coupled in parallel with the Josephson junction.

Abstract: A technique relates to a superconducting qubit. A Josephson junction includes a first superconductor and a second superconductor formed on a non-superconducting metal. A capacitor is coupled in parallel with the Josephson junction.

Abstract: Semiconductor devices and electronics packaging methods include integrated circuit chips having redundant signal bond pads along with signal bond pads connected to the same signal port for non-destructive testing of the integrated circuit chips prior to packaging. Electrical testing is made via the redundant signal bond after which qualified integrated circuit chips can be attached to a pristine and bumped final interposer or printed circuit board to provide increased reliability to the assembled electronic package.

Abstract: Semiconductor devices and electronics packaging methods include integrated circuit chips having redundant signal bond pads along with signal bond pads connected to the same signal port for non-destructive testing of the integrated circuit chips prior to packaging. Electrical testing is made via the redundant signal bond after which qualified integrated circuit chips can be attached to a pristine and bumped final interposer or printed circuit board to provide increased reliability to the assembled electronic package.

Abstract: A method for adjusting a qubit includes measuring a qubit characteristic of a qubit device and computing a modification to correct the qubit characteristic. A geometry of a shunt capacitor is adjusted using a laser direct write process. The qubit characteristic is verified.

Abstract: A semiconductor structure and methods of forming the semiconductor structure generally includes providing a thermocompression bonded superconducting metal layer sandwiched between a first silicon substrate and a second silicon substrate. The second substrate includes a plurality of through silicon vias to the thermocompression bonded superconducting metal layer. A second superconducting metal is electroplated into the through silicon vias using the thermocompression bonded superconducting metal layer as a bottom electrode during the electroplating process, wherein the filling is from the bottom upwards.

Abstract: A semiconductor structure and methods of forming the semiconductor structure generally includes providing a thermocompression bonded superconducting metal layer sandwiched between a first silicon substrate and a second silicon substrate. The second substrate includes a plurality of through silicon vias to the thermocompression bonded superconducting metal layer. A second superconducting metal is electroplated into the through silicon vias using the thermocompression bonded superconducting metal layer as a bottom electrode during the electroplating process, wherein the filling is from the bottom upwards.

Abstract: A semiconductor structure and methods of forming the semiconductor structure include a solder bump self-aligned to a through-substrate-via, wherein the solder bump and the through-substrate-via are formed of a conductive metal material, and wherein the through-substrate-via is coupled to a buried metallization layer, which is formed of a different conductive metal material.

Abstract: A semiconductor structure and methods of forming the semiconductor structure include a solder bump self-aligned to a through-substrate-via, wherein the solder bump and the through-substrate-via are formed of a conductive metal material, and wherein the through-substrate-via is coupled to a buried metallization layer, which is formed of a different conductive metal material.

Abstract: A system for adjusting qubit frequency includes a qubit device having a Josephson junction and a shunt capacitor coupled to electrodes of the Josephson junction. A cantilevered conductor is separated from the shunt capacitor by a spacing. An adjustment mechanism is configured to deflect the cantilevered conductor to tune a qubit frequency for the qubit device.

Abstract: A system for adjusting qubit frequency includes a qubit device having a Josephson junction and a shunt capacitor coupled to electrodes of the Josephson junction. A cantilevered conductor is separated from the shunt capacitor by a spacing. An adjustment mechanism is configured to deflect the cantilevered conductor to tune a qubit frequency for the qubit device.

Abstract: A microwave connector is provided. The microwave connector includes an outer conductor, an inner conductor disposed within the outer conductor and dielectric materials interposed between the outer conductor and the inner conductor, the dielectric materials including a non-dissipative dielectric material and a dissipative dielectric material.

Abstract: A system for adjusting qubit frequency includes a qubit device having a Josephson junction and a shunt capacitor coupled to electrodes of the Josephson junction. A cantilevered conductor is separated from the shunt capacitor by a spacing. An adjustment mechanism is configured to deflect the cantilevered conductor to tune a qubit frequency for the qubit device.

Abstract: A filter is provided and includes potting material formed into a body defining a through-hole. The body includes first and second opposing faces and a sidewall extending between the first and second opposing faces. The sidewall is formed to define first and second openings at opposite ends of the through-hole, first angles at an interface between the sidewall and the first face and second angles, which complement the first angles, at an interface between the sidewall and the second face.

Abstract: Embodiments are directed to a method of forming a conductive via. The method includes forming an opening in a substrate and forming a conductive material along sidewall regions of the opening, wherein the conductive material occupies a first portion of an area within the opening. The method further includes forming a conductive fill in a second portion of the area within the opening, wherein at least one surface of the conductive material and at least one surface of the conductive fill are substantially coplanar with a front surface of the substrate.

Abstract: Embodiments are directed to a method of forming a conductive via. The method includes forming an opening in a substrate and forming a conductive material along sidewall regions of the opening, wherein the conductive material occupies a first portion of an area within the opening. The method further includes forming an insulating fill in a second portion of the area within the opening, wherein at least one surface of the conductive material and at least one surface of the insulating fill are substantially coplanar with a front surface of the substrate.

Abstract: Embodiments are directed to a coupler system including a semiconductor wafer, an interconnect layer formed over the semiconductor wafer and a connector that is physically secured and electronically coupled to the interconnect layer. In one or more embodiments, the connector is physically secured and electronically coupled to the interconnect layer by a structure comprising an bond layer and an electrically conductive layer. In one or more embodiments, the structure is formed according to a methodology that includes forming a bond layer over the interconnect layer, forming the electrically conductive layer as a solder layer over the bond layer, and applying a reflow operation to at least the solder layer.