Abstract: An apparatus in accordance with one example includes a battery module in a dual in-line memory module (DIMM) form factor. The battery module is insertable in a DIMM slot of a host device to provide backup power to a plurality of loads of the host device.

Abstract: A printed circuit board (PCB) having a thermal relief pad around at least one via. The thermal relief pad includes at least four thermal cut-outs and at least four conductive bands. The at least four conductive bands are formed between the at least four thermal cut-outs such that adjacent conductive pads are orthogonal to each other. Each pair of mutually opposite conductive bands have substantially equal lengths and each pair of adjacent conductive bands have unequal lengths.

Abstract: The specification may disclose a computer system that may have two memory boards operated in a mirrored mode. The computer system may have the ability to operate in a mirrored mode with the memory boards having varying amounts of memory. This feature may allow for adding main memory to the computer system while the computer system is operational.

Abstract: The specification discloses a server system implementing hot pluggable memory boards in an architecture using X86 processors and off-the-shelf operating system, such as Windows® or Netware, which do not support hot plugging operations. Thus, the specification discloses systems and related methods for hot plugging main memory boards transparent to, and without the help of, the operating system. The operating system need only have the ability to recognize additional memory in order to use it. Moreover, the specification discloses a related set of memory error detection and correction techniques, again which are implementing transparent to, and without the help of, the operating system.

Abstract: A computer system implements hot mirroring for main system memory. That is, the computer system permits a user to hot plug a new memory board into the system and the system will respond by switching to a mirrored memory mode in which write cycles are performed to both memory boards (new and old). Once a new board is hot plugged into the system, the contents of the old board are copied over, in a background mode, to the new board so that both boards will have the same data. Because this background copying process may take a non-trivial amount of time and may detrimentally interfere with other system traffic, the system a user to exert control over the relative speed of the background copying so as to trade-off the time it takes to switch over to the mirroring mode versus the impact on on-going system behavior.

Abstract: A semiconductor package contains at least one electrically isolated channel. The isolated channel is minimally susceptible to crosstalk from other channels in the package. Specifically, the level of crosstalk that may impinge on the isolated channel is below an acceptable threshold so as to permit the isolated channel to function correctly. The semiconductor package may be a FET switch assembly and the isolated channel may be used for a clock signal to prevent crosstalk contamination caused by the data signals.

Abstract: A semiconductor package contains at least one electrically isolated channel. The isolated channel is minimally susceptible to crosstalk from other channels in the package. Specifically, the level of crosstalk that may impinge on the isolated channel is below an acceptable threshold so as to permit the isolated channel to function correctly. The semiconductor package may be a FET switch assembly and the isolated channel may be used for a clock signal to prevent crosstalk contamination caused by the data signals.

Abstract: The specification may disclose a computer system that may have two memory boards operated in a mirrored mode. The computer system may have the ability to operate in a mirrored mode with the memory boards having varying amounts of memory. This feature may allow for adding main memory to the computer system while the computer system is operational.

Abstract: A monitor provides analog conditioning circuitry for supplying a symmetrical high speed analog output signal generated from inverted and non-inverted digital data to imagers for a display of the monitor. The circuitry includes an upper bias amplifier for generating a precision upper DC offset signal. a lower bias amplifier for generating a precision lower DC offset signal, a switch for alternating selection of a precision DC offset signal with each frame, and a summing amplifier for adding the selected precision DC offset signal to a high speed analog signal provided by a digital-to-analog converter. Selection of the precision DC offset signal is controlled by an inversion signal provided to the switch from an inversion bit of a display controller. The digital data inversion is controlled by inversion circuitry within the display controller. The analog conditioning circuitry thus provides a single gain path and also provides low speed signal paths decoupled from a high speed signal path.

Abstract: The specification discloses a server system implementing hot pluggable memory boards in an architecture using X86 processors and off-the-shelf operating system, such as Windows® or Netware, which do not support hot plugging operations. Thus, the specification discloses systems and related methods for hot plugging main memory boards transparent to, and without the help of, the operating system. The operating system need only have the ability to recognize additional memory in order to use it. Moreover, the specification discloses a related set of memory error detection and correction techniques, again which are implementing transparent to, and without the help of, the operating system.

Abstract: A computer system implements hot mirroring for main system memory. That is, the computer system permits a user to hot plug a new memory board into the system and the system will respond by switching to a mirrored memory mode in which write cycles are performed to both memory boards (new and old). Once a new board is hot plugged into the system, the contents of the old board are copied over, in a background mode, to the new board so that both boards will have the same data. Because this background copying process may take a non-trivial amount of time and may detrimentally interfere with other system traffic, the system a user to exert control over the relative speed of the background copying so as to trade-off the time it takes to switch over to the mirroring mode versus the impact on on-going system behavior.

Abstract: Monitors for use in a tiled monitor system include adjacent monitor detectors arranged to detect the presence of corresponding adjacent monitor detectors on adjacent monitors so that the physical arrangements of the tiled monitors can be determined without user intervention. Similarly, orientation sensors are provided in each monitor so that their orientation—landscape vs. portrait—can be determined by the monitor without user intervention and reported to the video controller.

Abstract: A monitor provides automatic digital DC balancing for one or more imagers for a display of the monitor. The circuitry includes a filter for filtering one or more analog video signals, a microcontroller of the circuitry samples and digitizes the filtered analog video signal to generate a digital video signal. The microcontroller samples the filtered analog video signal for a portion of the display having known data values. The microcontroller then applies a digital filter to the digital video signal. The microcontroller detects a need for DC balancing by comparing the digital video signal in its upper operating range and its lower operating range with a digital reference DC signal corresponding to the DC signal level of the display. The circuitry further includes a digital potentiometer corresponding to each analog video signal. The microcontroller maintains DC balancing by providing a feedback signal to the digital potentiometers.

Abstract: A monitor provides analog conditioning circuitry for supplying a symmetrical high speed analog output signal generated from inverted and non-inverted digital data to imagers for a display of the monitor. The circuitry includes an upper bias amplifier for generating a precision upper DC offset signal. a lower bias amplifier for generating a precision lower DC offset signal, a switch for alternating selection of a precision DC offset signal with each frame, and a summing amplifier for adding the selected precision DC offset signal to a high speed analog signal provided by a digital-to-analog converter. Selection of the precision DC offset signal is controlled by an inversion signal provided to the switch from an inversion bit of a display controller. The digital data inversion is controlled by inversion circuitry within the display controller. The analog conditioning circuitry thus provides a single gain path and also provides low speed signal paths decoupled from a high speed signal path.

Abstract: A monitor having multiple video input ports and connectors is provided with automatic video input detection/selection circuitry. The circuitry may automatically detect when an external source such as a computer system is driving a video input port. The circuitry, for example, may detect whether a video input port is being driven by monitoring a sync signal (vertical or horizontal) for the video input port. A video input detect signal for a video input port may be generated from the sync signal for the video input port. In response to assertion of the video input detect signal indicating a source is driving a video input port, the circuitry may select the particular video input port. A microcontroller of the circuitry may provide a video input selector signal configured to select the video input port. When a single video input port is driven, user interaction is no longer necessary to select the particular video input port.

Abstract: A monitor provides analog conditioning circuitry for supplying a symmetrical high speed analog output signal generated from inverted and non-inverted digital data to imagers for a display of the monitor. The circuitry includes an upper bias amplifier for generating a precision upper DC offset signal, a lower bias amplifier for generating a precision lower DC offset signal, a switch for alternating selection of a precision DC offset signal with each frame, and a summing amplifier for adding the selected precision DC offset signal to a high speed analog signal provided by a digital-to-analog converter. Selection of the precision DC offset signal is controlled by an inversion signal provided to the switch from an inversion bit of a display controller. The digital data inversion is controlled by inversion circuitry within the display controller. The analog conditioning circuitry thus provides a single gain path and also provides low speed signal paths decoupled from a high speed signal path.