Patents by Inventor David W. Siljenberg
David W. Siljenberg has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10684319Abstract: Embodiments herein discuss tuning a testing apparatus to better match the input response of a target system in which a cable will be used. For example, conductors in the cable may have a different skew depending on the system in which they are used. The testing apparatus may be tuned using frequency information regarding the type of signals that will be driven on the cable when installed in the target system. In one embodiment, the testing apparatus adjusts a testing cycle refresh rate for generating a testing signal which changes the frequency content of the testing signal. Using the adjusted testing cycle refresh rate results in the driver outputting a testing signal that better reflects the actual signals that will be transmitted on the cable in the target system.Type: GrantFiled: July 20, 2015Date of Patent: June 16, 2020Assignee: International Business Machines CorporationInventors: Layne A. Berge, Benjamin A. Fox, Wesley D. Martin, David W. Siljenberg, George R. Zettles, IV
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Patent number: 10162002Abstract: Embodiments herein discuss tuning a testing apparatus to better match the input response of a target system in which a cable will be used. For example, conductors in the cable may have a different skew depending on the system in which they are used. The testing apparatus may be tuned using frequency information regarding the type of signals that will be driven on the cable when installed in the target system. In one embodiment, the testing apparatus uses the frequency information to configure a programmable clock source that can be used to shape a reference clock and control a driver to match the signals in the target system. Using the clock source to modify the reference clock results in the driver outputting a testing signal that better reflects the actual signals that will be transmitted on the cable in the target system.Type: GrantFiled: July 20, 2015Date of Patent: December 25, 2018Assignee: International Business Machines CorporationInventors: Layne A. Berge, Benjamin A. Fox, Wesley D. Martin, David W. Siljenberg, George R. Zettles, IV
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Patent number: 9712170Abstract: A level-shifting latch circuit for coupling a first circuit in a first voltage domain with a second circuit in a second voltage domain, includes an input node to receive an input signal provided by the first circuit, and an output node to output a level-shifted signal, corresponding with the input signal. The level-shifting latch circuit also includes a first latch, having a first node and a second node, for storing the input signal in the first voltage domain, and a second latch, having a third node and a fourth node, for storing the input signal in the second voltage domain. In addition, the level-shifting circuit also includes a first switching element which provides a path to transfer a low voltage at the first node to the third node, and a second switching element which provides a path to transfer a low voltage at the second node to the fourth node.Type: GrantFiled: December 24, 2014Date of Patent: July 18, 2017Assignee: International Bueinss Machines CorporationInventors: Anthony G. Aipperspach, Steven J. Baumgartner, Charles P. Geer, David P. Paulsen, David W. Siljenberg, Alan P. Wagstaff
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Patent number: 9583938Abstract: An electrostatic discharge (ESD) protection device to manage leakage current can, in response to a power good (PGOOD) signal, draw the gate terminal of an ESD clamp device to a voltage below ground. The device also drives an inverted copy of the PGOOD signal to a gated inverter, which can inhibit the gated inverter output from drawing the ESD clamp device gate terminal to ground. The ESD protection device also includes the ESD clamp device to, in response to the gate terminal of the ESD clamp device being drawn to a bias voltage less than ground, allow a leakage current to flow through the ESD clamp device that is less than a leakage current allowed to flow in response to the ESD clamp device gate terminal being drawn to ground.Type: GrantFiled: May 1, 2015Date of Patent: February 28, 2017Assignee: International Business Machines CorporationInventors: Anthony G. Aipperspach, Derick G. Behrends, Todd A. Christensen, David W. Siljenberg
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Publication number: 20170023646Abstract: Embodiments herein discuss tuning a testing apparatus to better match the input response of a target system in which a cable will be used. For example, conductors in the cable may have a different skew depending on the system in which they are used. The testing apparatus may be tuned using frequency information regarding the type of signals that will be driven on the cable when installed in the target system. In one embodiment, the testing apparatus uses the frequency information to configure a programmable clock source that can be used to shape a reference clock and control a driver to match the signals in the target system. Using the clock source to modify the reference clock results in the driver outputting a testing signal that better reflects the actual signals that will be transmitted on the cable in the target system.Type: ApplicationFiled: July 20, 2015Publication date: January 26, 2017Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Layne A. BERGE, Benjamin A. FOX, Wesley D. MARTIN, David W. SILJENBERG, George R. ZETTLES, IV
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Publication number: 20170023629Abstract: Embodiments herein discuss tuning a testing apparatus to better match the input response of a target system in which a cable will be used. For example, conductors in the cable may have a different skew depending on the system in which they are used. The testing apparatus may be tuned using frequency information regarding the type of signals that will be driven on the cable when installed in the target system. In one embodiment, the testing apparatus adjusts a testing cycle refresh rate for generating a testing signal which changes the frequency content of the testing signal. Using the adjusted testing cycle refresh rate results in the driver outputting a testing signal that better reflects the actual signals that will be transmitted on the cable in the target system.Type: ApplicationFiled: July 20, 2015Publication date: January 26, 2017Inventors: Layne A. BERGE, Benjamin A. FOX, Wesley D. MARTIN, David W. SILJENBERG, George R. ZETTLES, IV
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Patent number: 9553584Abstract: A level-shifting latch circuit for coupling a first circuit in a first voltage domain with a second circuit in a second voltage domain, includes an input node to receive an input signal provided by the first circuit, and an output node to output a level-shifted signal, corresponding with the input signal. The level-shifting latch circuit also includes a first latch, having a first node and a second node, for storing the input signal in the first voltage domain, and a second latch, having a third node and a fourth node, for storing the input signal in the second voltage domain. In addition, the level-shifting circuit also includes a first switching element which provides a path to transfer a low voltage at the first node to the third node, and a second switching element which provides a path to transfer a low voltage at the second node to the fourth node.Type: GrantFiled: December 23, 2014Date of Patent: January 24, 2017Assignee: International Business Machines CorporationInventors: Anthony G. Aipperspach, Steven J. Baumgartner, Charles P. Geer, David P. Paulsen, David W. Siljenberg, Alan P. Wagstaff
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Patent number: 9496712Abstract: An electrostatic discharge (ESD) protection device to manage leakage current can, in response to a power good (PGOOD) signal, draw the gate terminal of an ESD clamp device to a voltage below ground. The device also drives an inverted copy of the PGOOD signal to a gated inverter, which can inhibit the gated inverter output from drawing the ESD clamp device gate terminal to ground. The ESD protection device also includes the ESD clamp device to, in response to the gate terminal of the ESD clamp device being drawn to a bias voltage less than ground, allow a leakage current to flow through the ESD clamp device that is less than a leakage current allowed to flow in response to the ESD clamp device gate terminal being drawn to ground.Type: GrantFiled: April 1, 2016Date of Patent: November 15, 2016Assignee: International Business Machines CorporationInventors: Anthony G. Aipperspach, Derick G. Behrends, Todd A. Christensen, David W. Siljenberg
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Publication number: 20160322813Abstract: An electrostatic discharge (ESD) protection device to manage leakage current can, in response to a power good (PGOOD) signal, draw the gate terminal of an ESD clamp device to a voltage below ground. The device also drives an inverted copy of the PGOOD signal to a gated inverter, which can inhibit the gated inverter output from drawing the ESD clamp device gate terminal to ground. The ESD protection device also includes the ESD clamp device to, in response to the gate terminal of the ESD clamp device being drawn to a bias voltage less than ground, allow a leakage current to flow through the ESD clamp device that is less than a leakage current allowed to flow in response to the ESD clamp device gate terminal being drawn to ground.Type: ApplicationFiled: April 1, 2016Publication date: November 3, 2016Inventors: Anthony G. Aipperspach, Derick G. Behrends, Todd A. Christensen, David W. Siljenberg
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Publication number: 20160322812Abstract: An electrostatic discharge (ESD) protection device to manage leakage current can, in response to a power good (PGOOD) signal, draw the gate terminal of an ESD clamp device to a voltage below ground. The device also drives an inverted copy of the PGOOD signal to a gated inverter, which can inhibit the gated inverter output from drawing the ESD clamp device gate terminal to ground. The ESD protection device also includes the ESD clamp device to, in response to the gate terminal of the ESD clamp device being drawn to a bias voltage less than ground, allow a leakage current to flow through the ESD clamp device that is less than a leakage current allowed to flow in response to the ESD clamp device gate terminal being drawn to ground.Type: ApplicationFiled: May 1, 2015Publication date: November 3, 2016Inventors: Anthony G. Aipperspach, Derick G. Behrends, Todd A. Christensen, David W. Siljenberg
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Publication number: 20160182053Abstract: A level-shifting latch circuit for coupling a first circuit in a first voltage domain with a second circuit in a second voltage domain, includes an input node to receive an input signal provided by the first circuit, and an output node to output a level-shifted signal, corresponding with the input signal. The level-shifting latch circuit also includes a first latch, having a first node and a second node, for storing the input signal in the first voltage domain, and a second latch, having a third node and a fourth node, for storing the input signal in the second voltage domain. In addition, the level-shifting circuit also includes a first switching element which provides a path to transfer a low voltage at the first node to the third node, and a second switching element which provides a path to transfer a low voltage at the second node to the fourth node.Type: ApplicationFiled: December 24, 2014Publication date: June 23, 2016Inventors: Anthony G. Aipperspach, Steven J. Baumgartner, Charles P. Geer, David P. Paulsen, David W. Siljenberg, Alan P. Wagstaff
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Publication number: 20160182052Abstract: A level-shifting latch circuit for coupling a first circuit in a first voltage domain with a second circuit in a second voltage domain, includes an input node to receive an input signal provided by the first circuit, and an output node to output a level-shifted signal, corresponding with the input signal. The level-shifting latch circuit also includes a first latch, having a first node and a second node, for storing the input signal in the first voltage domain, and a second latch, having a third node and a fourth node, for storing the input signal in the second voltage domain. In addition, the level-shifting circuit also includes a first switching element which provides a path to transfer a low voltage at the first node to the third node, and a second switching element which provides a path to transfer a low voltage at the second node to the fourth node.Type: ApplicationFiled: December 23, 2014Publication date: June 23, 2016Inventors: Anthony G. Aipperspach, Steven J. Baumgartner, Charles P. Geer, David P. Paulsen, David W. Siljenberg, Alan P. Wagstaff
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Patent number: 9231796Abstract: Power aware equalization in a serial communications link that includes a transmitter and a receiver, including: determining, by a power aware equalization module, a required signal eye width and a required signal eye height for signals received by the receiver; identifying one or more signal equalizers for signals transmitted over the serial communications link; identifying one or more cumulative equalizer settings that equalize signals transmitted over the serial communications link to conform with the required signal eye width and the required signal eye height for signals received by the receiver; determining power consumption values associated with each of the one or more cumulative equalizer settings; and setting the one or more signal equalizers to configuration settings in dependence upon the power consumption values associated with each of the one or more cumulative equalizer settings.Type: GrantFiled: November 25, 2013Date of Patent: January 5, 2016Assignee: GLOBALFOUNDRIES Inc.Inventors: John F. Bulzacchelli, Hayden C. Cranford, Jr., Daniel M. Dreps, David W. Siljenberg
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Publication number: 20150146768Abstract: Power aware equalization in a serial communications link that includes a transmitter and a receiver, including: determining, by a power aware equalization module, a required signal eye width and a required signal eye height for signals received by the receiver; identifying one or more signal equalizers for signals transmitted over the serial communications link; identifying one or more cumulative equalizer settings that equalize signals transmitted over the serial communications link to conform with the required signal eye width and the required signal eye height for signals received by the receiver; determining power consumption values associated with each of the one or more cumulative equalizer settings; and setting the one or more signal equalizers to configuration settings in dependence upon the power consumption values associated with each of the one or more cumulative equalizer settings.Type: ApplicationFiled: November 25, 2013Publication date: May 28, 2015Applicant: International Business Machines CorporationInventors: John F. Bulzacchelli, Hayden C. Cranford, JR., Daniel M. Dreps, David W. Siljenberg
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Patent number: 7945805Abstract: A design structure for a high speed computer processor system includes a high speed interface for a graphics processor. In a preferred embodiment, the high speed interface includes a front side bus (FSB) that interfaces to a similar high speed interface on the graphics processor.Type: GrantFiled: October 31, 2007Date of Patent: May 17, 2011Assignee: International Business Machines CorporationInventors: Steven John Baumgartner, Anthony Richard Bonaccio, Timothy Clyde Buchholtz, Daniel Mark Dreps, Charles Porter Geer, Mounir Meghelli, Sergey Vladimirovich Rylov, David W. Siljenberg, Dana Marie Woeste
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Patent number: 7624297Abstract: A high speed computer processor system includes a high speed interface for a graphics processor. In a preferred embodiment, the high speed interface includes a front side bus (FSB) that interfaces to a similar high speed interface on the graphics processor.Type: GrantFiled: December 13, 2006Date of Patent: November 24, 2009Assignee: International Business Machines CorporationInventors: Steven John Baumgartner, Anthony Richard Bonaccio, Timothy Clyde Buchholtz, Daniel Mark Dreps, Charles Porter Geer, Mounir Meghelli, Sergey Vladimirovich Rylov, David W. Siljenberg, Dana Marie Woeste
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Publication number: 20090193372Abstract: A design structure comprising apparatus to equalize currents on a matching pair of FETs having sources connected together on a silicon on insulator semiconductor chip, or other chip wherein FET bodies can be individually biased. During a determination period, functional inputs coupled to the gates of the matching pair of FETs are short circuited, and a DAC adjusts a first body voltage of a first FET in the matching pair of FETs relative to a second body voltage of a second FET in the matching pair of FETs until a currents in the first FET and the second FET are equal, within resolution of the DAC's voltage granularity. A proper DAC control value is stored and applied to the DAC following the determination period when the short circuit is removed from the functional inputs.Type: ApplicationFiled: January 25, 2008Publication date: July 30, 2009Inventors: Steven John Baumgartner, David W. Siljenberg, Dana Marie Woeste
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Publication number: 20090189671Abstract: A method and apparatus to equalize currents on a matching pair of FETs having sources connected together on a silicon on insulator semiconductor chip, or other chip wherein FET bodies can be individually biased. During a determination period, functional inputs coupled to the gates of the matching pair of FETs are short circuited, and a DAC adjusts a first body voltage of a first FET in the matching pair of FETs relative to a second body voltage of a second FET in the matching pair of FETs until a currents in the first FET and the second FET are equal, within resolution of the DAC's voltage granularity. A proper DAC control value is stored and applied to the DAC following the determination period when the short circuit is removed from the functional inputs.Type: ApplicationFiled: January 25, 2008Publication date: July 30, 2009Inventors: Steven John Baumgartner, David W. Siljenberg, Dana Marie Woeste
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Publication number: 20080148088Abstract: A design structure for a high speed computer processor system includes a high speed interface for a graphics processor. In a preferred embodiment, the high speed interface includes a front side bus (FSB) that interfaces to a similar high speed interface on the graphics processor.Type: ApplicationFiled: October 31, 2007Publication date: June 19, 2008Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Steven John Baumgartner, Anthony Richard Bonaccio, Timothy Clyde Buchholtz, Daniel Mark Dreps, Charles Porter Geer, Mounir Meghelli, Sergey Vladimirovich Rylov, David W. Siljenberg, Dana Marie Woeste
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Publication number: 20080147952Abstract: A high speed computer processor system includes a high speed interface for a graphics processor. In a preferred embodiment, the high speed interface includes a front side bus (FSB) that interfaces to a similar high speed interface on the graphics processor.Type: ApplicationFiled: December 13, 2006Publication date: June 19, 2008Inventors: Steven John Baumgartner, Anthony Richard Bonaccio, Timothy Clyde Buchholtz, Daniel Mark Dreps, Charles Porter Geer, Mounir Meghelli, Sergey Vladimirovich Rylov, David W. Siljenberg, Dana Marie Woeste