Abstract: An eFuse reference cell on a chip provides a reference voltage that is greater than a maximum voltage produced by an eFuse cell having an unblown eFuse on the chip but less than a minimum voltage produced by an eFuse cell having a blown eFuse on the chip. A reference current flows through a resistor and an unblown eFuse in the eFuse reference cell, producing the reference voltage. The reference voltage is used to create a mirrored copy of the reference current in the eFuse cell. The mirrored copy of the reference current flows through an eFuse in the eFuse cell. A comparator receives the reference voltage and the voltage produced by the eFuse cell. The comparator produces an output logic level responsive to the voltage produced by the eFuse cell compared to the reference voltage.

Abstract: An apparatus and method is disclosed for transmitting signals over a signal conductor using a precompensated driver that does not use a current source, and which drives the signal conductor with an impedance similar to the characteristic impedance of the signal conductor. Since no current source is used, the precompensated driver can operate at very low supply voltage.

Abstract: A method and apparatus are provided for implementing power control in multi-voltage input/output (I/O) circuits. First current biasing devices are provided for creating a first constant bias current. Second current biasing devices are provided for creating a second bias current. The second current biasing devices are activated at a first voltage and are deactivated at a second voltage. The first voltage is less than the second voltage.

Abstract: A dual mode, analog differential and complementary metal oxide semiconductor (CMOS) logic circuit is provided. The circuit includes a differential input for receiving a differential input signal. A switch pair is coupled to the differential input. A pair of load resistors coupled to the switch pair defines a differential output for providing a differential output signal. A current source is coupled to the switch pair. A control input receives a control signal and control circuitry coupled to the control input disable the current source to select a CMOS testing mode responsive to the control signal being activated.

Abstract: Method and apparatus for testing a parallel optical transceiver are provided. One embodiment provides a built-in self-testing (BIST) parallel optical transceiver comprising a full-rate clock test pattern generator and a clock divider circuit connected to provide a half-rate clock signal to one of the one or more transmitter channels, and an error detector comprising one or more error detection circuits connected to one or more receiver channels and configured to receive the half-rate clock signal. Another embodiment provides a method for testing a parallel optical transceiver, comprising: generating a full-rate clock test pattern to one or more transmitter channels; providing a half-rate clock signal to one of the one or more transmitter channels utilizing a clock divider circuit; transmitting test pattern and half-rate clock signals to one or more corresponding receiver channels; and detecting error utilizing one or more error detection circuits connected to receive the half-rate clock signal.

Abstract: A fiber optic transceiver array is provided for implementing testing. The fiber optic transceiver array includes a plurality of sequential fiber optic transceiver channels. Each fiber optic transceiver channel includes a photodetector and has a predefined channel width. The photodetector of each sequential fiber optic transceiver channel is spaced apart substantially equal to the predefined channel width. A plurality of test pads is included in each fiber optic transceiver channel. A pair of power pads is included in each fiber optic transceiver channel. The predefined channel width and spacing between adjacent photodetectors is substantially equal to a spacing between fibers in a standard fiber optic cable. The plurality of test pads of each fiber optic transceiver channel includes a predefined sequence three test pads including a ground and a pair of differential channel outputs. Spacing between the differential channel outputs is minimized.

Abstract: Method and apparatus for testing a parallel optical transceiver are provided. One embodiment provides a built-in self-testing (BIST) parallel optical transceiver comprising a full-rate clock test pattern generator and a clock divider circuit connected to provide a half-rate clock signal to one of the one or more transmitter channels, and an error detector comprising one or more error detection circuits connected to one or more receiver channels and configured to receive the half-rate clock signal. Another embodiment provides a method for testing a parallel optical transceiver, comprising: generating a full-rate clock test pattern to one or more transmitter channels; providing a half-rate clock signal to one of the one or more transmitter channels utilizing a clock divider circuit; transmitting test pattern and half-rate clock signals to one or more corresponding receiver channels; and detecting error utilizing one or more error detection circuits connected to receive the half-rate clock signal.

Abstract: A charge pump that receives complimentary metal-oxide semiconductor (CMOS) input signals, has high noise immunity, low static error and works at low power supply voltages. The charge pump includes a current switch for receiving a control signal from a control circuit and for generating a charge signal, a loop filter having a first and second node, and a common-mode loop for sensing the charge signal from the current switch and for providing a voltage level adjustment signal to the first node of the loop filter in response thereto. The common-mode loop includes a sensing circuit for sensing the voltage level at the first and second node, an averaging circuit for producing an averaged voltage signal, a comparing circuit for comparing the averaged voltage signal to a reference signal to produce a feedback control output signal, and a feedback current source for adjusting the voltage level at the first node of the loop in response to the feedback control output signal.

Abstract: A fully redundant safety interlock system is provided comprising, means for detecting the loss of light on a fiber optic link; controller means, coupled to said means for detecting, for determining the safety condition of the link based on the output of said means for detecting, and for controlling the radiant energy output of an optical transmitter, based on the determined safety condition, via redundant output control signals; and means, coupled to said controller means, responsive to said redundant control signals, for interconnecting the output of said controller means to transmitter drive circuitry to thereby adjust the radiant energy output by the transmitter. According to a preferred embodiment of the invention, the controller means includes an electronic implementation of two independent state machines, each of which redundantly determines the connection state of the optical link between two optical link cards.

Abstract: An optical fiber link card communication module, and process for fabricating the module, where the module provides a parallel electrical interface to the user, facilitates high speed serial transmission of data over an optical data link, and contains a plurality of converters for performing conversions between both electrical and optical signals. A preferred embodiment of the invention contemplates fabricating the optical communication module on a single multilayer card with all the transmitter electrical components being located on one side of the card, all receiver electrical components being located on the other side of the card, and the transmitter and receiver components being separated by shielding layers in the card. By using two transmitter/receiver pairs (with the transmitters and receivers being located on respective sides of the card) an embodiment of the invention provides for double full duplex communications.

Abstract: An optical fiber link card communication module, and process for fabricating the module, where the module provides a parallel electrical interface to the user, facilitates high speed serial transmission of data over an optical data link, and contains a plurality of converters for performing conversions between both electrical and optical signals. The module further includes edge mounted optical components having leads mounted on the surface of a card (as opposed to standard pin-in-hole type leads) to minimize lead capacitance and inductance from the optical components to the card electronics, on board card control means for the converters and safety shut down means on the same card as the electrical and optical components.