Patents by Inventor David Wei
David Wei has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7973310Abstract: Semiconductor package structures and methods for manufacturing the same are provided. The semiconductor package structure comprises a substrate unit and a first chip stack structure. The substrate unit comprises a circuit structure having test pads. The first chip stack structure comprises chips, and each of the chips has a plurality of through silicon plugs. The through silicon plugs of two adjacent chips are electrically connected and further electrically connected to the test pads of the substrate unit for electrical testing. Another semiconductor package structure provided by the present invention comprises a first semiconductor chip and a second semiconductor chip. Each of the semiconductor chips has test pads for electrical testing and a plurality of through silicon plugs connecting to the test pads. The second semiconductor chip is mounted on the first semiconductor chip, and a portion of the through silicon plugs of two semiconductor chips are electrically connected with each other.Type: GrantFiled: July 10, 2009Date of Patent: July 5, 2011Assignee: Chipmos Technologies Inc.Inventors: David Wei Wang, An-Hong Liu, Hao-Yin Tsai, Hsiang-Ming Huang, Yi-Chang Lee, Shu-Ching Ho
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Publication number: 20110145144Abstract: An automated banking machine operates responsive to data read from data bearing records, such as user cards, to cause machine user authorization and financial transfers. Account data read from a user card is associated in a data store with instructions for displaying a customer interface uniquely associated with the particular bank where the user holds the account. The customer interface includes user-selectable financial transaction options. The arrangement enables the customer interface of the user's home bank, with which the user is familiar, to also be automatically displayed when the user operates automated banking machines of other banks.Type: ApplicationFiled: February 17, 2011Publication date: June 16, 2011Applicant: Diebold, IncorporatedInventors: Jay Paul Drummond, Bob A. Cichon, Mark D. Smith, David Weis
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Patent number: 7960214Abstract: A fabricating process of chip package structure is provided. First, a first substrate having a plurality of first bonding pads and a second substrate having a plurality of second bonding pads are provide, wherein a plurality of bumps are formed on the first bonding pads of the first substrate. A first two-stage adhesive layer is formed on the first substrate or on the second substrate and is B-stagized to form a first B-staged adhesive layer. A second two-stage adhesive layer is formed on the first B-staged adhesive layer and is B-stagized to form a second B-staged adhesive layer. Then, the first substrate and the second substrate are bonded via the first B-staged adhesive layer and the second B-staged adhesive layer such that each of the first bonding pads is respectively electrically connected to one of the second bonding pads via one of the bumps.Type: GrantFiled: July 8, 2008Date of Patent: June 14, 2011Assignees: ChipMOS Technologies Inc., ChipMOS Technologies (Bermuda) Ltd.Inventors: Geng-Shin Shen, David Wei Wang
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Publication number: 20110099219Abstract: Provided are techniques for, under control of an agent: receiving a request from a first database client to access a service from a set of services, wherein the agent is associated with the service; receiving a request from a second database client to access the service, wherein the agent is shared by the first database client and the second database client; combining information from the first database client and the second database client; and sending the combined information to the service using a single physical connection in a client-side Client Management Extension (CMX) connection, wherein the first database client and the second database client share the single physical connection.Type: ApplicationFiled: October 23, 2009Publication date: April 28, 2011Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: David Wei-Jye Chang, Bilung Lee, Paul A. Ostler
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Publication number: 20110068167Abstract: An automated banking machine includes an input device including a card reader which operates to read data bearing records in the form of user cards. The card data is usable to identify a user or a user account. The machine also includes an output device and a cash dispenser selectively operative to dispense currency sheets to machine users. Software operating in a computer of the machine causes the computer to operate a cash dispenser in carrying out cash dispensing transactions where cash is dispensed to users whose read accounts are assessed for value associated with cash dispensed. The computer also processes a mark up language document. The software includes screening software operative to prevent the computer from operating the cash dispenser responsive to communication with at least one system address.Type: ApplicationFiled: November 22, 2010Publication date: March 24, 2011Inventors: Jay Paul Drummond, Bob A. Cichon, Mark D. Smith, David Weis
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Patent number: 7892445Abstract: A method of dechucking a wafer, with a low-k dielectric layer, held onto an electrostatic chuck by an electrostatic charge in a plasma chamber is provided. The electrostatic clamping voltage is removed. An essentially argon free dechucking gas is provided into the plasma chamber. A dechucking plasma is formed from the dechucking gas in the plasma chamber. The dechucking plasma is stopped.Type: GrantFiled: September 12, 2007Date of Patent: February 22, 2011Assignee: Lam Research CorporationInventors: David Wei, Howard Dang, Masahiro Watanabe, Sean Kang, Kenji Takeshita, Mayumi Block, Stephen Sirard, Eric Hudson
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Publication number: 20110035580Abstract: A media access control (MAC) security (MACsec) function block may implement MACsec protocols on a network. A physical layer device (PHY) may connect to the MACsec function block and an interface register configured to store command information for the MACsec function block. A central processing unit (CPU) may provide the command information for the MACsec function block to the PHY via a management data input/output (MDIO) bus. The PHY may execute either a read command or a write command against the MACsec function block based on the command information, receive, from the MACsec function block, a response corresponding to the execution of the read command or write command against the MACsec function block, and provide the response to the CPU via the MDIO bus.Type: ApplicationFiled: September 17, 2009Publication date: February 10, 2011Applicant: Broadcom CorporationInventors: David (Wei) Wang, Daniel Tai
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Patent number: 7875548Abstract: Methods of fabricating semiconductor structures on a substrate, where the substrate has transistors formed thereon, are provided. One method includes forming interconnect metallization structures in a plurality of levels. The forming of the interconnect metallization structures includes depositing a sacrificial layer and performing a process to etch trenches, vias, and stubs into the sacrificial layer. The method further includes filling and planarizing the trenches, vias, and stubs that were etched and then etching away the sacrificial layer throughout the plurality of levels of the interconnect metallization structures. The etching leaving a voided interconnect metallization structure that is structurally supported by stubs that are non-electrically functional.Type: GrantFiled: August 7, 2008Date of Patent: January 25, 2011Assignee: Lam Research CorporationInventors: Yehiel Gotkis, David Wei, Rodney Kistler
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Patent number: 7866708Abstract: An apparatus includes a connector to connect a first tubing section and a second tubing section together. The connector that includes a body that includes a first opening to receive the first tubing section, a second opening to receive the second tubing section, and a passageway. The apparatus includes a member that is adapted to be moved from a retracted position to an extended position to form a sealed connection between a tubular member that is connected to the first tubing section and the passageway.Type: GrantFiled: March 9, 2004Date of Patent: January 11, 2011Assignee: Schlumberger Technology CorporationInventors: Craig D. Johnson, Matthew R. Hackworth, Michael D. Langlais, David Wei Wang, Laurent Alteirac, Stephane J. Virally, Jason Bigelow, Kerby J. Dufrene, Bruno Khan, Martin Prado, Ashish Sharma
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Patent number: 7870498Abstract: A method for visual programming an automated transaction machine (12). The method includes the creation of terminal directors (225) that generally correspond to transactions performed by the automated transaction machine. The terminal directors are programmed by visually creating associations (238) between a plurality of ATM objects (230, 232) in a work space (224). Exemplary ATM objects include an authorization object (260), a back stage control object (262), a card reader object (264), a customer profile object (266), a depositor object (268), a dispenser object (270), keypad object (272), a logic object (274), a OCS object (276), a presenter object (278), a PIN entry object (280), a printer object (282), a sync object (284), and a transaction data object (286). A portion of the exemplary ATM objects are operative to interface with a device interface layer (728) for communicating with physical hardware devices (724, 726).Type: GrantFiled: January 31, 2005Date of Patent: January 11, 2011Assignee: Diebold, IncorporatedInventors: Jay Paul Drummond, Bob A. Cichon, David Weis, James R. Church, Mikal R. Gilger, Jagadesh Myana, Todd Blakeslee, Aravind Dongara, Mark A. Moales, Randhika Bodapatla
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Patent number: 7847414Abstract: A chip package structure including a first substrate, a second substrate, a plurality of bumps, a first B-staged adhesive layer and a second B-staged adhesive layer is provided. The first substrate has a plurality of first bonding pads. The second substrate has a plurality of second bonding pads, and the second substrate is disposed above the first substrate. The bumps are disposed between the first substrate and the second substrate, wherein each of the first bonding pads is respectively electrically connected to one of the second bonding pads via one of the bumps. The first B-staged adhesive layer is adhered on the first substrate. The second B-staged adhesive layer is adhered between the first B-staged adhesive layer and the second substrate, wherein the first B-staged adhesive layer and the second B-staged adhesive layer encapsulate the bumps.Type: GrantFiled: June 27, 2008Date of Patent: December 7, 2010Assignees: ChipMOS Technologies Inc., ChipMOS Technologies (Bermuda) Ltd.Inventors: Geng-Shin Shen, David Wei Wang
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Patent number: 7798212Abstract: A technique is provided to facilitate connection of completion assemblies at a downhole location. A completion assembly comprises a control line conduit having a connector designed for coupling with a corresponding connector of a next adjacent completion assembly. A cover is selectively used to block entry of debris and other contaminants into the connector during deployment of the completion assembly downhole prior to engagement with the next adjacent completion of assembly.Type: GrantFiled: April 26, 2006Date of Patent: September 21, 2010Assignee: Schlumberger Technology CorporationInventors: Victor M. Bolze, David Wei Wang, Rex C. Mennem, David L. Verzwyvelt
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Patent number: 7789991Abstract: A method for etching features in a silicon oxide based dielectric layer over a substrate, comprising performing an etch cycle. A lag etch partially etching features in the silicon oxide based dielectric layer is performed, comprising providing a lag etchant gas, forming a plasma from the lag etchant gas, and etching the etch layer with the lag etchant gas, so that smaller features are etched slower than wider features. A reverse lag etch further etching the features in the silicon oxide based dielectric layer is performed comprising providing a reverse lag etchant gas, which is different from the lag etchant gas and is more polymerizing than the lag etchant gas, forming a plasma from the reverse lag etchant gas, and etching the silicon oxide based dielectric layer with the plasma formed from the reverse lag etchant gas, so that smaller features are etched faster than wider features.Type: GrantFiled: June 7, 2007Date of Patent: September 7, 2010Assignee: Lam Research CorporationInventors: Binet A. Worsham, Sean S. Kang, David Wei, Vinay Pohray, Bi Ming Yen
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Publication number: 20100205038Abstract: A method, system, and medium are provided for market intelligence tools for travel arrangements. A travel arrangement can be optimized by collecting and analyzing past event data for a desired travel selection. A data analysis engine aggregates, analyzes, and stores historical data of average travel ticket prices, as a function of the day of the year, for a travel selection. Another database analysis includes aggregating day-of-the-week data by the data analysis engine, wherein average travel ticket prices are given as a function of the day of the week, for both the departure day and the return day. Another database analysis includes aggregating advance purchase time data by the data analysis engine, wherein average travel ticket prices are given as a function of the number of days prior to a departure date. These database analyses are combined to form probabilities for the best and worst times to purchase travel tickets.Type: ApplicationFiled: February 10, 2009Publication date: August 12, 2010Applicant: MICROSOFT CORPORATIONInventors: JOHN MICHAEL RAUSER, JAMES THEODORE BARTOT, DAVID WEI HSU
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Patent number: 7749806Abstract: A fabricating process of a chip package structure is provided. First, a first substrate having a plurality of first bonding pads and a second substrate having a plurality of second bonding pads are provide, wherein a plurality of bumps are formed on the first bonding pads of the first substrate. A first two-stage adhesive layer is formed on the first substrate and is B-stagized to form a first B-staged adhesive layer. A second two-stage adhesive layer is formed on the second substrate and is B-stagized to form a second B-staged adhesive layer. Then, the first substrate and the second substrate are bonded via the first B-staged adhesive layer and the second B-staged adhesive layer such that each of the first bonding pads is respectively electrically connected to one of the second bonding pads via one of the bumps.Type: GrantFiled: July 8, 2008Date of Patent: July 6, 2010Assignees: ChipMOS Technologies Inc., ChipMOS Technologies (Bermuda) Ltd.Inventors: Geng-Shin Shen, David Wei Wang
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Publication number: 20100151624Abstract: A fabricating process of a chip package structure is provided. First, a first substrate having a plurality of first bonding pads and a second substrate having a plurality of second bonding pads are provided, wherein bumps are formed on the first bonding pads of the first substrate. A first two-stage adhesive layer is formed on the first substrate and is B-stagized to form a first B-staged adhesive layer. A second two-stage adhesive layer is formed on the second substrate and is B-stagized to form a second B-staged adhesive layer. Then, the first substrate and the second substrate are bonded via the first and second B-staged adhesive layer such that the bumps pierce through the second B-staged adhesive layer and are electrically connected to the second bonding pads, wherein each of the first bonding pads is respectively electrically connected to one of the second bonding pads via one of the bumps.Type: ApplicationFiled: March 1, 2010Publication date: June 17, 2010Applicants: CHIPMOS TECHNOLOGIES INC., CHIPMOS TECHNOLOGIES (BERMUDA) LTD.Inventors: Geng-Shin Shen, David Wei Wang
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Publication number: 20100088230Abstract: An automated banking machine operates responsive to data read from data bearing records, such as user cards, to cause machine user authorization and financial transfers. Account data read from a user card is associated in a data store with a server address, where a document is located. The document includes machine instructions for displaying a customer interface uniquely associated with the particular banking institution where the user holds the account. The customer interface includes user-selectable transaction options. The arrangement enables the customer interface of the user's home bank, with which the user is familiar, to also be automatically displayed to the user when the user operates automated banking machines of other banks.Type: ApplicationFiled: September 30, 2009Publication date: April 8, 2010Applicant: Diebold, IncorporatedInventors: Jay Paul Drummond, Bob A. Cichon, Mark D. Smith, David Weis
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Patent number: 7653601Abstract: A method of operating a cash dispensing automated banking machine includes causing through operation of a processor of a cash dispensing automated banking machine, a card reader of the machine to read data from a card which corresponds to an entity with which a customer operating the machine has an account. The method also includes providing through operation of the processor, at least one visual output through a display device on the automated banking machine, The visual output uniquely corresponds to the entity with which the customer has the account.Type: GrantFiled: January 12, 2005Date of Patent: January 26, 2010Assignee: Diebold, IncorporatedInventors: Jay Paul Drummond, Bob Cichon, Mark Smith, David Weis, James R. Church, Mikal R. Gilger
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Publication number: 20100012313Abstract: According to one or more aspects of the present disclosure, a piezoelectric pump may include a hydraulic fluid path between a low pressure source and a high pressure tool port; a fluid disposed in the hydraulic fluid path; a piston in communication with the fluid; and a piezoelectric material connected to the piston to pump the fluid through the high pressure tool port.Type: ApplicationFiled: July 17, 2009Publication date: January 21, 2010Applicant: SCHLUMBERGER TECHNOLOGY CORPORATIONInventors: Colin Longfield, David Wei Wang, Gary L. Rytlewski
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Publication number: 20100007001Abstract: Semiconductor package structures and methods for manufacturing the same are provided. The semiconductor package structure comprises a substrate unit and a first chip stack structure. The substrate unit comprises a circuit structure having test pads. The first chip stack structure comprises chips, and each of the chips has a plurality of through silicon plugs. The through silicon plugs of two adjacent chips are electrically connected and further electrically connected to the test pads of the substrate unit for electrical testing. Another semiconductor package structure provided by the present invention comprises a first semiconductor chip and a second semiconductor chip. Each of the semiconductor chips has test pads for electrical testing and a plurality of through silicon plugs connecting to the test pads. The second semiconductor chip is mounted on the first semiconductor chip, and a portion of the through silicon plugs of two semiconductor chips are electrically connected with each other.Type: ApplicationFiled: July 10, 2009Publication date: January 14, 2010Inventors: David Wei Wang, An-Hong Liu, Hao-Yin Tsai, Hsiang-Ming Huang, Yi-Chang Lee, Shu-Ching Ho