Abstract: A clock generator having a deskewer is disclosed. The clock generator includes a waveform generator and a deskewer. Clocked by an input clock signal, the waveform generator generates a waveform signal. The deskewer circuit, which is connected to the waveform generator, gates the waveform signal from the waveform generator with the input clock signal to produce an output clock signal such that the output clock signal has less skew with respect to the input clock signal.

Abstract: An apparatus for holding a first portion of a bone and a second portion of a bone together for the bone to heal. A method for holding a first portion of a bone and a second portion of a bone together for the bone to heal. A suture. A grommet for a bone. A method for securing a suture through a bone.

Abstract: An ultrasound system includes a transducer array having a plurality of transducer elements for transmitting ultrasound pulses and for receiving-echo pulses in response thereto, a circuit for energizing each transducer element, or batches of elements of the array, in turn, to generate an ultrasound pulse, and for receiving echo signals from at least two transducer elements resulting from transmission of an ultrasound pulse from another transducer element so that data used to create an image of the echo signals comes from the two transducer elements, a control device for controlling the order in which the transducers are energized and the order in which the transducers receive an echo pulse so as to carry out the energization and reception sequentially, a circuit for acquiring sequentially the data in analog form for a whole aperture, for acquiring sequentially the data for successive apertures and for processing the data for beam-formation for each aperture in correspondence with an analog echo pulse received

Abstract: The present invention provides for an electro-surgical instrument with a rich graphical user interface (GUI) capability and a verifiable hardware and software platform meeting Food and Drug Administration (FDA) requirements. The rich GUI makes for a device which is more easily operated than prior art devices which lacked a sophisticated user interface. The increased functionality is achieved without sacrificing the ability to validate the device for FDA purposes. This goal is achieved by a dual processor design. In the dual processor design a control or master processor with verifiable source code implements the functions of: power delivery, temperature measurement, power measurement and power control. A display or slave processor, is functionally isolated from the first processor receiving only messages from the first processor. In a first embodiment of the invention an electro-surgical instrument is disclosed.

Abstract: An integrated cache architecture that has low power consumption, high noise immunity, and full support of an integrated validity/least recently used (LRU) cache write mode. The cache stores TAG, index and LRU information directly on a master word line, and cache line data on local word lines. The access information is made available early in the cycle, allowing the cache to disable local word lines that are not needed. The master word lines and local word lines having approximately the same cycle time. By laying out the master and local word lines in a metal layer that substantially renders the stored data immune to overlaying noise sources, high frequency interconnections can be made over the cache without disturbing the stored data. The architecture circuitry efficiently updates the stored LRU information, such that a combined data validity/full LRU cache update protocol is supported.

Abstract: An integrated cache architecture that has low power consumption, high noise immunity, and full support of an integrated validity/LRU cache write mode. The cache stores TAG, index and LRU information directly on a master word line, and cache line data on local word lines. The access information is made available early in the cycle, allowing the cache to disable local word lines that are not needed. By laying out the master and local word lines in a metal layer that substantially renders the stored data immune to overlaying noise sources, high frequency interconnections can be made over the cache without disturbing the stored data. The cache includes circuitry for efficiently updating the stored LRU information, such that a combined data validity/full LRU cache update protocol is supported.

Abstract: Apparatus for loading live poultry into open-topped containers (19) comprise a plurality (preferably three) loading units (28) arranged side by side so that each loading unit (28) is aligned with a column of containers (19) accommodated in a standard module (18). Each loading unit has a batching receptacle (33) to receive a batch of poultry (of predetermined weight or number) corresponding to the capacity of one of the open-topped containers (19) which are in turn withdrawn from the module (18), loaded with a batch of poultry and then returned to the module, each loading unit (28) shifting vertically as successive containers are loaded with poultry. A separate catching vehicle (54) may be used to catch the poultry and deliver it to the apparatus.

Abstract: Apparatus for loading live poultry into open-topped containers (19) comprise a plurality (preferably three) loading units (28) arranged side by side so that each loading unit (28) is aligned with a column of containers (19) accommodated in a standard module (18). Each loading unit has a batching receptacle (33) to receive a batch of poultry (of predetermined weight or number) corresponding to the capacity of one of the open-topped containers (19) which are in turn withdrawn from the module (18), loaded with a batch of poultry and then returned to the module, each loading unit (28) shifting vertically as successive containers are loaded with poultry. A separate catching vehicle (54) may be used to catch the poultry and deliver it to the apparatus.

Abstract: An integrated cache architecture that has low power consumption, high noise immunity, and full support of an integrated validity/LRU cache write mode. A first plurality of memory cells coupled to the master word lines stores access information corresponding to a plurality of data words stored in a second plurality a memory cells coupled to a plurality of local word lines. The cache stores tag, index and Least Recently Used (LRU) information directly on a master word line, and cache line data on local word lines. The access information is made available early in the cycle, allowing the cache to disable local word lines that are not needed. By laying out the master and local word lines in a metal layer that substantially renders the stored data immune to overlaying noise sources, high frequency interconnections can be made over the cache without disturbing the stored data.