Abstract: Embodiments of present invention provide a semiconductor structure. The semiconductor structure includes a deep trench via in a double diffusion region between a first dummy metal gate and a second dummy metal gate; a frontside metal wire conductively connected to a top surface of the deep trench via through a frontside via; and a backside metal wire conductively connected to a bottom surface of the deep trench via through a backside via and a backside contact, where the frontside metal wire and the backside metal wire are not vertically aligned but parallel to each other, and directions of the frontside and backside metal wires are orthogonal to a length direction of the deep trench via. A method of forming the same is also provided.

Abstract: An approach to forming a semiconductor device where the semiconductor device includes a first power rail that is connected to a decoupling capacitor by way of a first gate. The decoupling capacitor is also connected to a second gate. As such, the decoupling capacitor separates the first gate from the second gate. The decoupling capacitor may include a dielectric liner within a gate cut trench and a ferroelectric material over the dielectric liner. A second power rail may be connected to the decoupling capacitor by way of the second gate. The first gate and the second gate may be inline with respect thereto.

Abstract: Method and structures for shared (dual) sources for a single device in semiconductor devices such as very-large-scale integration (VLSI) devices. The shared-source improves or increases a current that passes through the device (e.g., to a drain region associated with the shared-source), which in turn increases a performance of the device. Example improvements may include a delay improvement of the device and associated logic paths and/or a power improvement for the device. The method includes operations for design improvements during a design process by implementing shared-sources in a semiconductor device design.

Abstract: Embodiments of the present disclosure provide methods, systems, and computer program products for implementing intelligent timing aware metal fill optimization for an IC layout. The disclosed methods enable fill tooling to identify the existing metal tile density and provide timing-aware metal fill insertion to specifically target density requirements and enable effective timing characteristics of signal path nets.

Abstract: Embodiments of the present disclosure provide methods, systems, and computer program products for implementing retargeting-aware metal fill optimization for an IC layout. A disclosed embodiment enables a metal fill optimization design tool to identify empty space adjacent to the active metal shapes of one or more signal path nets in a metal shapes infrastructure and provide retargeting-aware metal fill insertion into empty space configured to specifically avoid foundry retargeting operations having adverse impacts on timing characteristics of signal path nets.

Abstract: A semiconductor structure includes a first field-effect transistor having a first back side source/drain contact, a second back side source/drain contact, and a first power line and a first signal line each connected to the first back side source/drain contact and the second back side source/drain contact, respectively. The semiconductor structure further includes a second field-effect transistor vertically stacked above the first field-effect transistor. The second field-effect transistor having a first front side source/drain contact, a second front side source/drain contact, and a first power line and a first signal line each connected to the first front side source/drain contact and the second front side source/drain contact, respectively.

Abstract: Embodiments of present invention provide a semiconductor structure. The semiconductor structure includes a metal level that includes a metal line, the metal line includes a bottom section having a first width, a middle section having a second width, and a top section having a third width, where the second width of the middle section is narrower than the first width of the bottom section and is narrower than the third width of the top section. A method of forming the semiconductor structure is also provided.

Abstract: A semiconductor interconnect structure and formation thereof. The semiconductor interconnect structure includes a first set of metal lines running along a first orientation, and a second set of metal lines having an insulating liner and running along a second orientation. The second set of metal lines are embedded within the first set of metal lines at respective cross points between the first and second set of metal lines, such that the second set of metal lines are located in a same metal level as the first set of metal lines.

Abstract: A semiconductor device includes a gate metal and a gate extension disposed within a region between two transistors of opposite conductivity and connected to the gate metal. The gate extension extends toward a side of the semiconductor device having power rails. A gate cut is disposed within the gate metal and through the gate extension to cut the gate extension into portions that are electrically isolated from each other. Each of the portions of the gate extension is coupled to a backside power rail.

Abstract: A semiconductor device includes a first stacked field-effect transistor structure having a first lower field-effect transistor device and a first upper field-effect transistor device. The semiconductor device also includes a second stacked field-effect transistor structure comprising a second lower field-effect transistor device and a second upper field-effect transistor device, where at least one of: the first lower field-effect transistor device includes a different number of channel layers than the second lower field-effect transistor device; and the first upper field-effect transistor device includes a different number of channel layers than the second upper field-effect transistor device.

Abstract: Embodiments herein describe thermal transfer vias and via structures of a semiconductor structure, and methods for implementing thermal transfer vias and via structures for enhanced thermal transfer in the semiconductor structure of integrated circuit designs. A disclosed thermal transfer via comprises a conductive material for thermally transferring heat, and a via structure comprises at least one thermal transfer via providing enhanced thermal transfer in the semiconductor structure of an integrated circuit design.

Abstract: A semiconductor structure comprises a first device layer, a second device layer, and a plurality of interconnect wiring levels between the first device layer and the second device layer. The plurality of interconnect wiring levels comprise a first interconnect wiring level adjacent the first device layer, wherein wires of the first interconnect wiring level are spaced apart from each other at a first pitch, a second interconnect wiring level adjacent the second device layer, wherein wires of the second interconnect wiring level are spaced apart from each other at a second pitch, and at least a third interconnect wiring level between the first interconnect wiring level and the second interconnect wiring level, wherein wires of the third interconnect wiring level are spaced apart from each other at a third pitch. The third pitch is greater than the first pitch and the second pitch.

Abstract: A semiconductor device includes an active region layer having source/drain regions laterally disposed relative to one another in a row and having a zone bounded between adjacent source/drain regions. An embedded jumper is electrically connected to two adjacent source/drain regions within the zone.

Abstract: A semiconductor structure includes a substrate, one or more nanosheet channel layers disposed over the substrate, and a dielectric bar attached to the one or more nanosheet channel layers, where the dielectric bar is not perpendicular to the substrate. The one or more nanosheet channel layers include a first set of one or more nanosheet channels attached to a first side of the dielectric bar and a second set of one or more nanosheet channels attached to a second side of the dielectric bar.

Abstract: A field effect transistor (FET) device is provided. The FET device includes an active region and a gate. The active region includes a source at a first end of the active region and a drain at a second end of the active region. The gate extends across the active region and includes at least one end extending past a corresponding edge of the active region by a sub-lithographic dimension.

Abstract: Embodiments of present invention provide a semiconductor structure. The semiconductor structure includes a first device layer on top of a backside back-end-of-line (BEOL) structure; a middle BEOL structure on top of the first device layer, the middle BEOL structure including multiple layers of small pitch wires and multiple layers of large pitch wires on top of the multiple layers of small pitch wires; a second device layer on top of the middle BEOL structure; a frontside BEOL structure on top of the second device layer; a first type via connection from the second device layer to the multiple layers of small pitch wires; and a second type and a third type via connection form the second device layer to the multiple layers of large pitch wires. A method of forming the same is also provided.

Abstract: Embodiments herein describe techniques for identifying excess antennas (or antenna diodes) in a IC design using computer software tools. An IC design can be changed for any number of reasons, which can change the number of antennas that are required to sufficiently protect the IC from damage during the fabrication process. Currently, a chip designer would use a ratio to determine whether a portion of the IC (e.g., a macro) has too many or too few antennas. The embodiments herein describe techniques where computer software tools identify excess antennas for the designer. The designer can then decide whether to remove these antennas. In another embodiment, the computer software tools may automatically remove some or all of the identified excess antennas, without input from the chip designer.

Abstract: A hierarchical integrated circuit design includes at least an upper hierarchy level, an intermediate hierarchy level, and a lower hierarchy level. The lower hierarchy level includes a design entity including an antenna diode. Processing circuitry of a data processing system performs placement for integrated circuitry bounded by the design entity.

Abstract: Method and apparatus for generating an updated power delivery network. Generating the power delivery network includes determining power characteristics for a power delivery network of a circuit design based on logic cells of the circuit design. The power delivery network includes power wires and power staples connecting pairs of the power wires to each other. Further a first one or more of the power staples is remove from the power delivery network based on the power characteristics. Signal wires for the logic cells are routed after removing the first one or more of the power staples. Routing the signal wires includes routing a first signal wire of the signal wires in a routing track corresponding to the first one or more of the power staples.

Abstract: A capacitive memory cell includes an electrode, a tunneling barrier layer in direct contact with the electrode, a charge trapping layer in direct contact with the tunneling barrier layer, a ferroelectric layer in direct contact with the charge trapping layer, and another electrode in direct contact with the ferroelectric layer.