Abstract: Using unused wires on VLSI chips for power supply decoupling including generating a VLSI chip design by: identifying floating wires in a VLSI chip; placing a via at each intersection between each floating wire and a power rail; determining a number of design rule violations for each via at each intersection; resolving the design rule violations for each via not on a major power rail; resolving the design rule violations for each via on a major power rail after resolving the design rule violations for each via not on a major power rail; after resolving the design rule violations for each via on a major power rail, identifying floating wires without a via; and for each floating wire without a via, identify an intersection with a least number of design rule violations and resolve the number of design rule violations by removing adjacent vias on adjacent wires.

Abstract: A technique relates to structuring a semiconductor device. First empty cells are placed against hierarchical boundaries of a macro block. Functional cells are added in the macro block. Remaining areas are filled with second empty cells in the macro block. Shape requirements are determined for the first empty cells and the second empty cells. The first and second empty cells are replaced with determined shape requirements.

Abstract: Embodiments of the invention are directed to methods, systems, and computer program products for the hierarchical management of self-aligned double patterning (SADP) trim shapes. Non-limiting embodiments of the invention include receiving, by a processor, one or more virtual trim shapes at a boundary between a parent hierarchy block and a child hierarchy block. The trim shapes are aligned to a legal trim grid. The processor then places one or more trim shapes aligned with the legal trim grid.

Abstract: Using unused wires on VLSI chips for power supply decoupling including generating a VLSI chip design by: identifying floating wires in a VLSI chip; placing a via at each intersection between each floating wire and a power rail; determining a number of design rule violations for each via at each intersection; resolving the design rule violations for each via not on a major power rail; resolving the design rule violations for each via on a major power rail after resolving the design rule violations for each via not on a major power rail; after resolving the design rule violations for each via on a major power rail, identifying floating wires without a via; and for each floating wire without a via, identify an intersection with a least number of design rule violations and resolve the number of design rule violations by removing adjacent vias on adjacent wires.

Abstract: Using unused wires on VLSI chips for power supply decoupling including generating a VLSI chip design by: identifying floating wires in a VLSI chip; placing a via at each intersection between each floating wire and a power rail; determining a number of design rule violations for each via at each intersection; resolving the design rule violations for each via not on a major power rail; resolving the design rule violations for each via on a major power rail after resolving the design rule violations for each via not on a major power rail; after resolving the design rule violations for each via on a major power rail, identifying floating wires without a via; and for each floating wire without a via, identify an intersection with a least number of design rule violations and resolve the number of design rule violations by removing adjacent vias on adjacent wires.

Abstract: Using unused wires on VLSI chips for power supply decoupling including generating a VLSI chip design by: identifying floating wires in a VLSI chip; placing a via at each intersection between each floating wire and a power rail; determining a number of design rule violations for each via at each intersection; resolving the design rule violations for each via not on a major power rail; resolving the design rule violations for each via on a major power rail after resolving the design rule violations for each via not on a major power rail; after resolving the design rule violations for each via on a major power rail, identifying floating wires without a via; and for each floating wire without a via, identify an intersection with a least number of design rule violations and resolve the number of design rule violations by removing adjacent vias on adjacent wires.

Abstract: A technique relates to structuring a semiconductor device. First empty cells are placed against hierarchical boundaries of a macro block. Functional cells are added in the macro block. Remaining areas are filled with second empty cells in the macro block. Shape requirements are determined for the first empty cells and the second empty cells. The first and second empty cells are replaced with determined shape requirements.

Abstract: Embodiments of the invention are directed to methods, systems, and computer program products for the hierarchical management of self-aligned double patterning (SADP) trim shapes. Non-limiting embodiments of the invention include receiving, by a processor, one or more virtual trim shapes at a boundary between a parent hierarchy block and a child hierarchy block. The trim shapes are aligned to a legal trim grid. The processor then places one or more trim shapes aligned with the legal trim grid.

Abstract: A method for determining that a circuit is operating in the reverse temperature dependence domain includes creating baseline delay information, detecting a temperature change with one or more temperature sensors, after detecting the temperature change, creating current delay information, comparing the baseline delay information with the current delay information, determining that the temperature change was a positive change; determining that the current delay information indicates that the circuit is operating faster when the baseline delay information was taken.

Abstract: A training simulation method and system for training operational service units such as call centre or customer service centres personnel are provided, including providing a simulated scenario to personnel, the scenario progressing in scenario time and the scenario including a plurality of simulated events provided in a predetermined sequence in real time at predetermined scenario times within the scenario, and receiving responses to the events from personnel. The system can simulate scenarios, which unfold to personnel in real time, and the responses of the personnel can be received in real time, so adding to the realism of the simulation being provided. The personnel responses can be marked and assessed to give a competency rating for their responses.