Abstract: In accordance with one embodiment, an apparatus is provided, comprising: a double data rate (DDR) memory controller that, when in operation, causes the apparatus to: capture a data bit input signal in a first core domain register that is communicatively coupled to a second core domain register; clock the first core domain register utilizing a first clock; clock the second core domain register utilizing a second clock; maintain a difference in time between an active edge of the second clock and a next active edge of the first clock, such that the difference in time corresponds to a capture clock delay value; and set the capture clock delay value during a power-on initialization calibration operation.

Abstract: Systems and methods are provided for combining a plurality of streams with a plurality of formats into a single output stream in a predetermined output format. Each of the plurality of streams includes at least one of video or graphics. Each stream is processed by determining a format of the stream, determining whether the format is compatible with the predetermined output format, and responsive to determining that the format is compatible with the predetermined output format, converting the format to the predetermined output format. The processed plurality of streams are combined into a single output stream in the predetermined output format.

Abstract: In some aspects, the disclosure is directed to methods and systems for transformation between media formats, such as between standard dynamic range (SDR) and high dynamic range (HDR) media or between HDR media formats, without undesired hue shifting, via one or both of a luminance mapping ratio technique and a direct color component mapping technique.

Abstract: Systems for providing isolation of a bias signal relative to a radio frequency (RF) signal in an integrated circuit, and related circuits, modules, and methods, are disclosed herein. In one example embodiment, a system includes an inductor, a bypass capacitor, and a transmission line segment, which includes first and second ends and extends between the first and second ends. The first end is at least indirectly coupled to the bypass capacitor, the second end is at least indirectly coupled to a first additional end of the inductor, and a second additional end of the inductor is configured to be coupled at least indirectly to a device through which the RF signal is being communicated. The transmission line segment is configured to impart a non-negligible phase shift to a signal communicated between the first and second ends, or is configured to have a non-negligible effective inductance.

Abstract: In accordance with one embodiment, a computer-implemented method is provided, comprising: configuring code to cause at least part of hardware to operate as a double data rate (DDR) memory controller and to produce one or more capture clocks, where: a timing of at least one of the one or more capture clocks is based on a first clock signal of a first clock, the first clock signal is a core clock signal or a signal derived from at least the core clock signal, the at least one of the one or more capture clocks is used to time a read data path, the at least one of the one or more capture clocks is used to capture read data into a clock domain related to a second clock, the first clock and the second clock being related in timing such that at least one of: the second clock is derived from the first clock, or the first clock is derived from the second clock; and providing access to the code.

Abstract: An amplifier module is provided. The amplifier module includes a multi-layer printed circuit board (PCB). A first power transistor die is mounted at a top surface of the multi-layer PCB. A second power transistor die is mounted at the top surface of the multi-layer PCB. An impedance inversion element is coupled between an output of the first power transistor die and an output of the second power transistor die. A combining node is formed at the output of the second power transistor die. A stub circuit including a transmission line element is coupled at the combining node.

Abstract: An amplifier module is provided. The amplifier module includes a multi-layer printed circuit board (PCB). A first power transistor die is mounted at a top surface of the multi-layer PCB. A second power transistor die is mounted at the top surface of the multi-layer PCB. An impedance inversion element is coupled between an output of the first power transistor die and an output of the second power transistor die. A combining node is formed at the output of the second power transistor die. A stub circuit including a transmission line element is coupled at the combining node.

Abstract: An embodiment of a module (e.g., an amplifier module) includes a substrate, a transmission line, and a ground plane height variation structure. The substrate is formed from a plurality of dielectric material layers, and has a mounting surface and a second surface opposite the mounting surface. A plurality of non-overlapping zones is defined at the mounting surface. The transmission line is coupled to the substrate and is located within a first zone of the plurality of non-overlapping zones. The ground plane height variation structure extends from the second surface into the substrate within the first zone. The ground plane height variation structure underlies the transmission line, a portion of the substrate is present between the upper boundary and the transmission line, and the ground plane height variation structure includes a conductive path between an upper boundary of the ground plane height variation structure and the second surface.

Abstract: An information handling system operating a forced data leakage prevention system may comprise a processor executing code instructions of the forced data leakage prevention system to identify a third party application and an associated first dynamic link library address, identify a control policy associated with the third party application and the identified user, wherein the control policy includes a subset of code instructions associated with a secure data set, identify a call to execute code instructions stored at the first dynamic link library address, move the code instructions stored at the first dynamic link library into a second library prior to execution, inject the subset of code instructions into the code instructions stored in the second library according to the control policy, and move the code instructions stored in the second library including the injected subset of code instructions into the first dynamic link library for execution by the processor.

Abstract: Systems and methods are provided to render a plurality of graphical assets each having a format of a plurality of formats. Each graphical asset is processed by determining whether the format of the graphical asset is compatible with a predetermined render domain format and responsive to determining the format is not compatible with the predetermined render domain format, converting, using a format conversion circuit, the format to the predetermined render domain format. The plurality of graphical assets are rendered using a single rendering engine operable coupled to the format conversion circuit using the predetermined render domain format.

Abstract: A system for lossless switching of traffic in a network device may be implemented when a network switch is integrated into a gateway device, or with any other data source. A processor of the gateway device may receive queue depth information for queues of the network switch. The processor may prevent data from being transmitted to congested queues of the network switch, while allowing data to be transmitted to uncongested queues. In this manner, data loss can be avoided through the network switch for data sourced from the gateway device, such as audio-video data retrieved from a hard drive, audio-video data received from a tuner, etc. Furthermore, re-transmission at higher layers can be reduced. Since the subject system observes congestion for each individual queue, only traffic destined to that particular, congested, queue is affected, e.g. paused. Traffic to non-congested queues is not affected, regardless of traffic class or egress port.

Abstract: A method and system for enhancing a cognitive ability may comprise conducting, via a user interface display of a user computing device, a training session which may comprise presenting, via the user interface display of the user computing device, a variable stimuli go/no-go behavior response exercise, which may comprise establishing an assembly platform containing an outline of component parts of a final assembled item; presenting a plurality of component delivery platforms; delivering a component corresponding to at least one of the plurality of components of the final assembled item to at least one of the component delivery platforms; allowing the user to select or not select the component on the at least one of the plurality of component delivery platforms according to at least one selection criteria; and scoring the correctness of the user selecting or not selecting the component according to the at least one selection criteria.

Abstract: A Doherty amplifier module includes first and second amplifier die. The first amplifier die includes one or more first power transistors configured to amplify, along a first signal path, a first input RF signal to produce an amplified first RF signal. The second amplifier die includes one or more second power transistors configured to amplify, along a second signal path, a second input RF signal to produce an amplified second RF signal. A phase shift and impedance inversion element is coupled between the outputs of the first and second amplifier die. A shunt circuit is coupled to the output of either or both of the first and/or second amplifier die. The shunt circuit includes a series coupled inductance and high-Q capacitor (e.g., a metal-insulator-metal (MIM) capacitor), and the shunt circuit is configured to at least partially resonate out the output capacitance of the amplifier die to which it is connected.

Abstract: In accordance with one embodiment, an apparatus is provided, comprising: a double data rate (DDR) memory controller that, when in operation, causes the apparatus to: capture a data bit input signal in a first core domain register that is communicatively coupled to a second core domain register; clock the first core domain register utilizing a first clock; clock the second core domain register utilizing a second clock; maintain a difference in time between an active edge of the second clock and a next active edge of the first clock, such that the difference in time corresponds to a capture clock delay value; and set the capture clock delay value during a power-on initialization calibration operation.

Abstract: Embodiments of a multiple-path amplifier (e.g., a Doherty amplifier) and a module housing the amplifier include a first amplifier (or first power transistor die) with a first output terminal, a second amplifier (or second power transistor die) with a second output terminal, and an impedance inverter line assembly electrically connected between the first and second output terminals. The impedance inverter line assembly includes a first transmission line and a surface mount component connected in series between the first and second output terminals. In various embodiments, the surface mount component is selected from a fixed-value capacitor, a fixed-value inductor, a tunable capacitor, a tunable inductor, and a tunable passive component network.

Abstract: An apparatus for improved rendering includes a number of processing channels to receive multiple input content sources and to process that input content. A compositor can composite processed input content to generate a composite output signal. An output adaptation block can adapt the composite output signal along with dynamic metadata for display by a display device. Each processing channel includes a statistics generator and an input adaptation block.

Abstract: In the subject system for video warping, an electronic device may receive video data (e.g., from a video source). The electronic device may also receive or generate control information including view configuration information (e.g., for one or more viewports). The electronic device may warp a subset of the video data according to the view configuration information. The electronic device may process the warped subset of the video data using metadata associated with the video data. The electronic device may provide, for display, the processed subset of the video data. By warping the subset of the video data and then processing the warped subset of the video data, the system performs processing on the subset of the video data, instead of performing the processing the entire video data. In addition, the warped video data may be at a lower resolution than the original video data, which may require less resources for processing.

Abstract: In some aspects, the disclosure is directed to methods and systems for transformation between media formats, such as between standard dynamic range (SDR) and high dynamic range (HDR) media or between HDR media formats, without undesired hue shifting, via one or both of a luminance mapping ratio technique and a direct color component mapping technique.