Patents by Inventor David Yeh
David Yeh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240085449Abstract: An electronic device may include a housing and a display in the housing. The display may be used as an anemometer to measure the speed of ambient air in the device's environment. In particular, the display may be monitored by a temperature sensor until it reaches an equilibrium temperature, at which point it may be heated by increasing the brightness of the display or using a separate heater. After heating, a cooling response of the display may be measured, and the ambient air speed may be calculated based on the cooling response of the display. Instead of measuring the air speed using the display, other components, such as a pressure sensor, may be used to measure the air speed by heating the components and measuring a cooling response of the components. Multiple temperature sensors may be incorporated into the device to determine a wind direction in addition to air speed.Type: ApplicationFiled: July 11, 2023Publication date: March 14, 2024Inventors: David MacNeil, Michael J. Glickman, John P. Bergen, Richard Yeh
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Publication number: 20230299087Abstract: Two or more types of fin-based transistors having different gate structures and formed on a single integrated circuit are described. The gate structures for each type of transistor are distinguished at least by the thickness or composition of the gate dielectric layer(s) or the composition of the work function metal layer(s) in the gate electrode. Methods are also provided for fabricating an integrated circuit having at least two different types of fin-based transistors, where the transistor types are distinguished by the thickness and composition of the gate dielectric layer(s) and/or the thickness and composition of the work function metal in the gate electrode.Type: ApplicationFiled: April 28, 2023Publication date: September 21, 2023Inventors: Curtis TSAI, Chia-Hong JAN, Jeng-Ya David YEH, Joodong PARK, Walid M. HAFEZ
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Publication number: 20230283447Abstract: RF systems configured to implement full-duplex wireless data transfer for rotary joints are disclosed. An example RF system includes a 60 GHz short distance communication link implemented using elliptically (e.g., circularly) polarized antennas. Such a system may provide a mm-wave, high-speed, wideband wireless communication link in a manner that is associated with simpler design and operation, mechanical integrity, and reduced power consumption, compared to alternative solutions.Type: ApplicationFiled: May 8, 2023Publication date: September 7, 2023Inventors: Mohamed Alaaeldin Moharram Hassan, Po-Hao David.A Yeh, Mark A. D′Amato, Anton Patyuchenko, John N. Poelker, Christopher P. O’Neill, Omar El Sayed Wadah
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Publication number: 20230274725Abstract: An adaptive noise cancelling system utilizing a plurality of multi-axis accelerometers and a plurality of microphones, wherein the plurality of multi-axis accelerometers and the plurality microphones may be used in combination to pick up vibrations on a chassis of a vehicle. The accelerometers may be positioned at point near the suspension knuckles or joints of the vehicle, and the microphones may be positioned near the headrest and sun visor of the vehicle. The adaptive noise cancelling system may use an adaptive algorithm to derive one or more filter weights that model a transfer function between the vibrations on the chassis of the vehicle to an acoustic pressure at the plurality of microphones location.Type: ApplicationFiled: July 27, 2021Publication date: August 31, 2023Inventors: David Yeh, Tzu-Sheng Hsu
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Publication number: 20230268406Abstract: A method includes forming a semiconductor fin over a substrate; forming a gate structure over the semiconductor fin, the gate structure comprising: a first metallic layer; a second metallic layer over the first metallic layer, wherein the first metallic layer is a metal compound of a first element and a second element and the second metallic layer is a single-element metal of the second element; and an oxide layer between the first metallic layer and the second metallic layer.Type: ApplicationFiled: April 24, 2023Publication date: August 24, 2023Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Hsin-Che CHIANG, Ju-Yuan TZENG, Chun-Sheng LIANG, Chih-Yang YEH, Shu-Hui WANG, Jeng-Ya David YEH
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Patent number: 11695008Abstract: Two or more types of fin-based transistors having different gate structures and formed on a single integrated circuit are described. The gate structures for each type of transistor are distinguished at least by the thickness or composition of the gate dielectric layer(s) or the composition of the work function metal layer(s) in the gate electrode. Methods are also provided for fabricating an integrated circuit having at least two different types of fin-based transistors, where the transistor types are distinguished by the thickness and composition of the gate dielectric layer(s) and/or the thickness and composition of the work function metal in the gate electrode.Type: GrantFiled: April 13, 2020Date of Patent: July 4, 2023Assignee: Intel CorporationInventors: Curtis Tsai, Chia-Hong Jan, Jeng-Ya David Yeh, Joodong Park, Walid M. Hafez
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Patent number: 11689344Abstract: Radio Frequency (RF) systems configured to implement full-duplex wireless data transfer for rotary joints are disclosed. An example RF system includes a 60 GHz short distance communication link implemented using elliptically (e.g., circularly) polarized antennas. Such a system may provide a mm-wave, high-speed, wideband wireless communication link in a manner that is associated with simpler design and operation, mechanical integrity, and reduced power consumption, compared to alternative solutions.Type: GrantFiled: April 9, 2021Date of Patent: June 27, 2023Assignee: ANALOG DEVICES INTERNATIONAL UNLIMITED COMPANYInventors: Mohamed Alaaeldin Moharram Hassan, Po-Hao David A. Yeh, Mark A. D'Amato, Anton Patyuchenko, John N. Poelker, Christopher P. O'Neill, Omar El Sayed Wadah
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Patent number: 11670697Abstract: A semiconductor device includes a substrate comprising a semiconductor fin, a gate structure over the semiconductor fin, and source/drain structures over the semiconductor fin and on opposite sides of the gate structure. The gate stack comprises a high-k dielectric layer; a first work function metal layer over the high-k dielectric layer; an oxide of the first work function metal layer over the first work function metal layer; and a second work function metal layer over the oxide of the first work function metal layer, in which the first and second work function metal layers have different compositions; and a gate electrode over the second work function metal layer.Type: GrantFiled: June 21, 2021Date of Patent: June 6, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Hsin-Che Chiang, Ju-Yuan Tzeng, Chun-Sheng Liang, Chih-Yang Yeh, Shu-Hui Wang, Jeng-Ya David Yeh
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Publication number: 20230111553Abstract: In a method of manufacturing a semiconductor device, first and second gate structures are formed. The first (second) gate structure includes a first (second) gate electrode layer and first (second) sidewall spacers disposed on both side faces of the first (second) gate electrode layer. The first and second gate electrode layers are recessed and the first and second sidewall spacers are recessed, thereby forming a first space and a second space over the recessed first and second gate electrode layers and first and second sidewall spacers, respectively. First and second protective layers are formed in the first and second spaces, respectively. First and second etch-stop layers are formed on the first and second protective layers, respectively. A first depth of the first space above the first sidewall spacers is different from a second depth of the first space above the first gate electrode layer.Type: ApplicationFiled: December 5, 2022Publication date: April 13, 2023Inventors: Hsiang-Ku SHEN, Chih Wei Lu, Hui-Chi Chen, Jeng-Ya David Yeh
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Patent number: 11521970Abstract: In a method of manufacturing a semiconductor device, first and second gate structures are formed. The first (second) gate structure includes a first (second) gate electrode layer and first (second) sidewall spacers disposed on both side faces of the first (second) gate electrode layer. The first and second gate electrode layers are recessed and the first and second sidewall spacers are recessed, thereby forming a first space and a second space over the recessed first and second gate electrode layers and first and second sidewall spacers, respectively. First and second protective layers are formed in the first and second spaces, respectively. First and second etch-stop layers are formed on the first and second protective layers, respectively. A first depth of the first space above the first sidewall spacers is different from a second depth of the first space above the first gate electrode layer.Type: GrantFiled: October 5, 2020Date of Patent: December 6, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Hsiang-Ku Shen, Chih Wei Lu, Hui-Chi Chen, Jeng-Ya David Yeh
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Patent number: 11264380Abstract: A semiconductor device includes a substrate, a first active fin, a second active fin, a dummy fin and a first gate structure. The first and the second active fin are on the substrate and extend along a first direction. The dummy fin is disposed between the first active fin and the second active fin, and extends in the first direction. The dummy fin includes a plurality of layers, and each of the layers includes a material different from another layer. The first gate structure crosses over the dummy fin, the first and the second active fins.Type: GrantFiled: August 27, 2018Date of Patent: March 1, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Hou-Ju Li, Chur-Shyang Fu, Chun-Sheng Liang, Jeng-Ya David Yeh
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Publication number: 20210351901Abstract: RF systems configured to implement full-duplex wireless data transfer for rotary joints are disclosed. An example RF system includes a 60 GHz short distance communication link implemented using elliptically (e.g., circularly) polarized antennas. Such a system may provide a mm-wave, high-speed, wideband wireless communication link in a manner that is associated with simpler design and operation, mechanical integrity, and reduced power consumption, compared to alternative solutions.Type: ApplicationFiled: April 9, 2021Publication date: November 11, 2021Applicant: Analog Devices International Unlimited CompanyInventors: Mohamed Alaaeldin Moharram HASSAN, Po-Hao David A. YEH, Mark A. D'AMATO, Anton PATYUCHENKO, John N. POELKER, Christopher P. O'NEILL, Omar El Sayed WADAH
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Patent number: 11145730Abstract: A semiconductor device includes a substrate, a first gate structure, a plurality of first gate spacers, a second gate structure, and a plurality of second gate spacers. The substrate has a first fin structure and a second fin structure. The first gate structure is over the first fin structure, in which the first gate structure includes a first high dielectric constant material and a first metal. A bottom surface of the first high dielectric constant material is higher than bottom surfaces of the first gate spacers. The second gate structure is narrower than the first gate structure and over the second fin structure, in which the second gate structure includes a second high dielectric constant material and a second metal. A bottom surface of the second high dielectric constant material is lower than bottom surfaces of the second gate spacers.Type: GrantFiled: November 8, 2019Date of Patent: October 12, 2021Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Hsin-Che Chiang, Ju-Yuan Tzeng, Chun-Sheng Liang, Shu-Hui Wang, Chih-Yang Yeh, Jeng-Ya David Yeh
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Publication number: 20210313437Abstract: A semiconductor device includes a substrate comprising a semiconductor fin, a gate structure over the semiconductor fin, and source/drain structures over the semiconductor fin and on opposite sides of the gate structure. The gate stack comprises a high-k dielectric layer; a first work function metal layer over the high-k dielectric layer; an oxide of the first work function metal layer over the first work function metal layer; and a second work function metal layer over the oxide of the first work function metal layer, in which the first and second work function metal layers have different compositions; and a gate electrode over the second work function metal layer.Type: ApplicationFiled: June 21, 2021Publication date: October 7, 2021Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Hsin-Che CHIANG, Ju-Yuan TZENG, Chun-Sheng LIANG, Chih-Yang YEH, Shu-Hui WANG, Jeng-Ya David YEH
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Patent number: 11043567Abstract: A semiconductor device includes a substrate, a gate stack. The substrate includes a semiconductor fin. The gate stack is disposed on the semiconductor fin. The gate stack includes a dielectric layer disposed over the semiconductor fin, and a metal stack disposed over the dielectric layer and having a first metallic layer and a second metallic layer over the first metallic layer, and a gate electrode disposed over the metal stack. The first metallic layer and the second metallic layer have a first element, and a percentage of the first element in the first metallic layer is greater than that in the second metallic layer.Type: GrantFiled: August 28, 2018Date of Patent: June 22, 2021Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Hsin-Che Chiang, Ju-Yuan Tzeng, Chun-Sheng Liang, Chih-Yang Yeh, Shu-Hui Wang, Jeng-Ya David Yeh
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Publication number: 20210020633Abstract: In a method of manufacturing a semiconductor device, first and second gate structures are formed. The first (second) gate structure includes a first (second) gate electrode layer and first (second) sidewall spacers disposed on both side faces of the first (second) gate electrode layer. The first and second gate electrode layers are recessed and the first and second sidewall spacers are recessed, thereby forming a first space and a second space over the recessed first and second gate electrode layers and first and second sidewall spacers, respectively. First and second protective layers are formed in the first and second spaces, respectively. First and second etch-stop layers are formed on the first and second protective layers, respectively. A first depth of the first space above the first sidewall spacers is different from a second depth of the first space above the first gate electrode layer.Type: ApplicationFiled: October 5, 2020Publication date: January 21, 2021Inventors: Hsiang-Ku SHEN, Chih Wei LU, Hui-Chi CHEN, Jeng-Ya David YEH
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Patent number: 10854607Abstract: An impurity source film is formed along a portion of a non-planar semiconductor fin structure. The impurity source film may serve as source of an impurity that becomes electrically active subsequent to diffusing from the source film into the semiconductor fin. In one embodiment, an impurity source film is disposed adjacent to a sidewall surface of a portion of a sub-fin region disposed between an active region of the fin and the substrate and is more proximate to the substrate than to the active area.Type: GrantFiled: April 20, 2020Date of Patent: December 1, 2020Assignee: Intel CorporationInventors: Chia-Hong Jan, Walid M Hafez, Jeng-Ya David Yeh, Hsu-Yu Chang, Neville L Dias, Chanaka D Munasinghe
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Patent number: 10825907Abstract: A semiconductor device and a method of forming the semiconductor device is disclosed. A sacrificial film is used to pattern a contact to a semiconductor structure, such as a contact to a source/drain region of a transistor. The contact may include a tapered profile along an axis parallel to the gate electrode such that an outermost width of the contact decreases as the contact extends away from the source/drain region.Type: GrantFiled: July 30, 2018Date of Patent: November 3, 2020Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Tung Ying Lee, Chih Chieh Yeh, Jeng-Ya David Yeh, Yuan-Hung Chiu, Chi-Wen Liu, Yee-Chia Yeo
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Patent number: 10797048Abstract: In a method of manufacturing a semiconductor device, first and second gate structures are formed. The first (second) gate structure includes a first (second) gate electrode layer and first (second) sidewall spacers disposed on both side faces of the first (second) gate electrode layer. The first and second gate electrode layers are recessed and the first and second sidewall spacers are recessed, thereby forming a first space and a second space over the recessed first and second gate electrode layers and first and second sidewall spacers, respectively. First and second protective layers are formed in the first and second spaces, respectively. First and second etch-stop layers are formed on the first and second protective layers, respectively. A first depth of the first space above the first side wall spacers is different from a second depth of the first space above the first gate electrode layer.Type: GrantFiled: January 12, 2018Date of Patent: October 6, 2020Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Hsiang-Ku Shen, Chih Wei Lu, Janet Chen, Jeng-Ya David Yeh
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Patent number: 10755970Abstract: In one exemplary aspect, a method for semiconductor manufacturing comprises forming first and second silicon nitride features on sidewall surfaces of a contact hole, where the contact hole is disposed in a dielectric layer and above a source/drain (S/D) feature. The method further comprises forming a contact plug in the contact hole, the contact plug being electrically coupled to the S/D feature, removing a top portion of the contact plug to create a recess in the contact hole, forming a hard mask layer in the recess, and removing the first and second silicon nitride features via selective etching to form first and second air gaps, respectively.Type: GrantFiled: June 15, 2018Date of Patent: August 25, 2020Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Hsin-Che Chiang, Ju-Li Huang, Chun-Sheng Liang, Jeng-Ya David Yeh