Abstract: A method of reading an eFuse in a column of eFuse memory cells includes electrically disconnecting a first end of the eFuse from a first electrical path. A second electrical path between a second end of the eFuse and a node is activated to bypass a third electrical path, where the third electrical path includes a diode device between the second end of the eFuse and the node. A footer coupled with the node is turned on.

Abstract: An embodiment is an integrated circuit (IC) structure. The structure comprises a deep n well in a substrate, a first pickup device in the deep n well, a first signal device in the deep n well, a dissipation device in the substrate, a second signal device in the substrate, a first electrical path between the first pickup device and the dissipation device, and a second electrical path between the first signal device and the second signal device. The dissipation device is outside of the deep n well, and the second signal device is outside of the deep n well. A highest point of the first electrical path is lower than a highest point of the second electrical path.

Abstract: The embodiments of methods and structures disclosed herein provide mechanisms of forming and programming a non-salicided polysilicon fuse. The non-salicided polysilicon fuse and a programming transistor form a one-time programmable (OTP) memory cell, which can be programmed with a low programming voltage.

Abstract: Methods, systems, and apparatus, including computer programs encoded on a computer storage medium, for receiving a search query, identifying a plurality of search results that are responsive to the search query, the plurality of search results including a plurality of items of digital content distributed using one or more social networking services, and determining that one or more terms provided in the search query is an active keyword and, in response: defining a first sub-set of items, the first sub-set of items including items of the plurality of items of digital content and being responsive to the active keyword, and providing items in the first sub-set of items for display as a discussion stream within search results.

Abstract: During various processing operations, ions from process plasma may be transfer to a deep n-well (DNW) formed under devices structures. A reverse-biased diode may be connected to the signal line to protect a gate dielectric formed outside the DNW and is connected to the drain of the transistor formed inside the DNW.

Abstract: A method of reading an eFuse in a column of eFuse memory cells includes electrically disconnecting a first end of the eFuse from a first electrical path. A second electrical path between a second end of the eFuse and a node is activated to bypass a third electrical path, where the third electrical path includes a diode device between the second end of the eFuse and the node. A footer coupled with the node is turned on.

Abstract: An input of a first inverter is configured to serve as an input node. An output of the first inverter is coupled to an input of a second inverter. An output of the second inverter is configured to serve as an output node. An input of a third inverter is coupled to an input of the first inverter. A gate of a first NMOS transistor is coupled to an output of the third inverter. A drain of the first NMOS transistor is coupled to the second inverter. A source of the first NMOS transistor is configured to serve as a level input node. When the input node is configured to receive a low logic level, the output node is configured to receive a voltage level provided by a voltage level at the level input node.

Abstract: An embodiment is an integrated circuit (IC) structure. The structure comprises a deep n well in a substrate, a first pickup device in the deep n well, a first signal device in the deep n well, a dissipation device in the substrate, a second signal device in the substrate, a first electrical path between the first pickup device and the dissipation device, and a second electrical path between the first signal device and the second signal device. The dissipation device is outside of the deep n well, and the second signal device is outside of the deep n well. A highest point of the first electrical path is lower than a highest point of the second electrical path.

Abstract: Some embodiments regard a memory array that has a plurality of rows and columns. A column includes a program control device, a plurality of eFuse memory cells in the column, a sense amplifier, and a bit line coupling the program control device, the plurality of memory cells in the column, and the sense amplifier. A row includes a plurality of eFuse memory cells in the row, a word line coupling the plurality of eFuse memory cells in the row, and a footer configured as a current path for the plurality of eFuse memory cells in the row.

Abstract: A system and method which may allow a Web application to manage cookies and prevent important data in cookies from being arbitrarily deleted. Cookie data may be separated into a number of tiers according to their importance. When a request to write new data to a cookie is received, the tier to which the new data belongs may be determined and compared to the tier(s) of existing data in the cookie, and existing data may be deleted from the cookie to free room for the new data only when the existing data is not more important than the new data.

Abstract: The invention discloses improved processes to halogenate polymers. In particular, the invention discloses to improved processes to halogenate polymers made from C4-1012 isoolefins.

Abstract: The embodiments of methods and structures disclosed herein provide mechanisms of forming and programming a non-salicided polysilicon fuse. The non-salicided polysilicon fuse and a programming transistor form a one-time programmable (OTP) memory cell, which can be programmed with a low programming voltage.

Abstract: The invention provides for processes to produce elastomeric compositions, the processes including contacting at least one elastomer with a processing aid, wherein the processing aid includes the reaction product of at least one functionalized polymer having at least one anhydride group contacted with at least one polyamine, wherein the at least one polyamine includes at least one primary amine. The invention also provides for articles such as innerliners for tires produced from the aforementioned elastomeric compositions.

Abstract: The invention provides for processes to produce elastomeric compositions, the processes including contacting at least one elastomer with a processing aid, wherein the processing aid comprises at least one functionalized polymer having at least one halogen group. The invention also provides for articles such as innerliners for tires produced from the aforementioned elastomeric compositions.

Abstract: An input of a first inverter is configured to serve as an input node. An output of the first inverter is coupled to an input of a second inverter. An output of the second inverter is configured to serve as an output node. An input of a third inverter is coupled to an input of the first inverter. A gate of a first NMOS transistor is coupled to an output of the third inverter. A drain of the first NMOS transistor is coupled to the second inverter. A source of the first NMOS transistor is configured to serve as a level input node. When the input node is configured to receive a low logic level, the output node is configured to receive a voltage level provided by a voltage level at the level input node.

Abstract: Some embodiments regard a memory array that has a plurality of rows and columns. A column includes a program control device, a plurality of eFuse memory cells in the column, a sense amplifier, and a bit line coupling the program control device, the plurality of memory cells in the column, and the sense amplifier. A row includes a plurality of eFuse memory cells in the row, a word line coupling the plurality of eFuse memory cells in the row, and a footer configured as a current path for the plurality of eFuse memory cells in the row.

Abstract: A memory cell includes a write access transistor coupled between a storage node and a write bit line, and active during a write cycle responsive to a voltage on a write word line; a read access transistor coupled between a read word line and a read bit line, and active during a read cycle responsive to a voltage at the storage node; and a storage capacitor coupled between the read word line and the storage node. Methods for operating the memory cell are also disclosed.

Abstract: The invention provides for processes to produce elastomeric compositions, the processes including contacting at least one elastomer with a processing aid, wherein the processing aid comprises at least one functionalized polymer having at least one anhydride group. The invention also provides for articles such as innerliners for tires produced from the aforementioned elastomeric compositions.

Abstract: The invention discloses improved processes to halogenate polymers. In particular, the invention discloses to improved processes to halogenate polymers made from C4-1012 isoolefins.

Abstract: A system and method which may allow a Web application to manage cookies and prevent important data in cookies from being arbitrarily deleted. Cookie data may be separated into a number of tiers according to their importance. When a request to write new data to a cookie is received, the tier to which the new data belongs may be determined and compared to the tier(s) of existing data in the cookie, and existing data may be deleted from the cookie to free room for the new data only when the existing data is not more important than the new data.