Abstract: A system and method for measuring optical properties of films deposited or formed on semiconductor wafers. Measurements of an optical property are made in a plurality of non-overlapping locations within a test region of a film at a low radiation dose, and the measurements are averaged. The radiation dose is less than the actinic radiation sensitivity dose of the film, so that chemical changes in the film are not caused by the measurements. The measurements may be calibrated to prior art methods, and the results may be adjusted by the adjustment or calibration factor.

Abstract: A technique is provided to define a pattern (100) on a substrate (70) that includes a dense region with a number of features (101) and an isolated feature region comprised of at least a part of one of the features (101). The dense feature region has a greater feature density than the isolated feature region. A reference feature (103) is measured at a number of different points relative to the isolated feature region and the dense feature region with a measurement tool (75). An iso-dense effect is determined from these measurements.

Abstract: A technique is provided to define a pattern (100) on a substrate (70) that includes a dense region with a number of features (101) and an isolated feature region comprised of at least a part of one of the features (101). The dense feature region has a greater feature density than the isolated feature region. A reference feature (103) is measured at a number of different points relative to the isolated feature region and the dense feature region with a measurement tool (75). An iso-dense effect is determined from these measurements.

Abstract: Methods and apparatus for calculating alignment of layers during semiconductor processing are described. In one embodiment, first and second alignment targets are formed over a substrate and include respective pairs of first and second alignment target edges. The second alignment target defines a point of reference. First and second distances are measured between the first alignment target edges and the second alignment target edges as respective first and second functions of the distance from the point of reference. The first and second functions are differenced to define a linear equation having a slope and ii an intercept which contains offset components in two different directions. In a preferred embodiment, third and fourth alignment targets are formed over the substrate, with the fourth alignment target defining a different point of reference.

Abstract: Methods and structures for determining alignment during semiconductor wafer processing are described. In one implementation, two geometric shapes are formed at different elevations over a substrate and at least partially overlapping with one another. The two shapes are inspected for overlap to determine whether the two shapes are misaligned. If the shapes are misaligned, a magnitude of misalignment is determined from the degree of overlap of the two shapes. In another implementation, a pair of elevationally spaced-apart geometric shapes are used to translate shifts of the shapes in one direction into quantifiable shift magnitudes using another direction. In yet another implementation, shifts in both the X and Y direction are readily quantifiable through visual inspection.

Abstract: A method for facilitating alignment measurements in a semiconductor fabrication process that uses a combination of underlying and latent images on a substrate to indicate alignment between a lithographic mask and the substrate. In an example embodiment of the method for measuring alignment, a substrate has a layer of photoresist disposed on it is illuminated through a reticle element resulting in the formation of a first plurality of underlying grating images. The first plurality of images has a repetitive and symmetrical pattern with equal spacing between images. A second plurality of latent grating images is formed in the photoresist having substantially the same pattern of images as the first plurality of images. The second plurality of images is disposed above from the first plurality of images, the first and second plurality of images serving as an indicator of alignment between the mask and the substrate when the combined images forming a repetitive pattern.

Abstract: Methods and structures for determining alignment during semiconductor wafer processing are described. In one implementation, two geometric shapes are formed at different elevations over a substrate and at least partially overlapping with one another. The two shapes are inspected for overlap to determine whether the two shapes are misaligned. If the shapes are misaligned, a magnitude of misalignment is determined from the degree of overlap of the two shapes. In another implementation, a pair of elevationally spaced-apart geometric shapes are used to translate shifts of the shapes in one direction into quantifiable shift magnitudes using another direction. In yet another implementation, shifts in both the X and Y direction are readily quantifiable through visual inspection.

Abstract: Methods and structures for determining alignment during semiconductor wafer processing are described. In one implementation, two geometric shapes are formed at different elevations over a substrate and at least partially overlapping with one another. The two shapes are inspected for overlap to determine whether the two shapes are misaligned. If the shapes are misaligned, a magnitude of misalignment is determined from the degree of overlap of the two shapes. In another implementation, a pair of elevationally spaced-apart geometric shapes are used to translate shifts of the shapes in one direction into quantifiable shift magnitudes using another direction. In yet another implementation, shifts in both the X and Y direction are readily quantifiable through visual inspection.

Abstract: A semiconductor device is manufactured using an ashing process to eliminate the adverse effects of contamination, such as amine-airborne contamination. Consistent with one embodiment of the present invention, the semiconductor device is formed by applying a DUV-type photoresist over the wafer surface, exposing the photoresist to DUV light, baking the wafer, and then ashing the wafer in a highly-oxidized environment to remove insoluble amine-related resist.

Abstract: Methods and apparatus for calculating alignment of layers during semiconductor processing are described. In one embodiment, first and second alignment targets are formed over a substrate and include respective pairs of first and second alignment target edges. The second alignment target defines a point of reference. First and second distances are measured between the first alignment target edges and the second alignment target edges as respective first and second functions of the distance from the point of reference. The first and second functions are differenced to define a linear equation having a slope and ii an intercept which contains offset components in two different directions. In a preferred embodiment, third and fourth alignment targets are formed over the substrate, with the fourth alignment target defining a different point of reference.

Abstract: Methods and structures for determining alignment during semiconductor wafer processing are described. In one implementation, two geometric shapes are formed at different elevations over a substrate and at least partially overlapping with one another. The two shapes are inspected for overlap to determine whether the two shapes are misaligned. If the shapes are misaligned, a magnitude of misalignment is determined from the degree of overlap of the two shapes. In another implementation, a pair of elevationally spaced-apart geometric shapes are used to translate shifts of the shapes in one direction into quantifiable shift magnitudes using another direction. In yet another implementation, shifts in both the X and Y direction are readily quantifiable through visual inspection.

Abstract: Methods and apparatus for calculating alignment of layers during semiconductor processing are described. In one embodiment, first and second alignment targets are formed over a substrate and include respective pairs of first and second alignment target edges. The second alignment target defines a point of reference. First and second distances are measured between the first alignment target edges and the second alignment target edges as respective first and second functions of the distance from the point of reference. The first and second functions are differenced to define a linear equation having a slope and an intercept which contains offset components in two different directions. In a preferred embodiment, third and fourth alignment targets are formed over the substrate, with the fourth alignment target defining a different point of reference.

Abstract: A semiconductor device is manufactured using an acid treatment process to eliminate the adverse effects of contamination, such as amine-airborne contamination. Consistent with one embodiment of the present invention, the semiconductor device is formed by applying a DUV-type photoresist over the wafer surface, exposing the photoresist to DUV light, treating the exposed photoresist with an acid vapor, and thereafter baking the exposed wafer.

Abstract: A semiconductor fabrication process permits for narrowing linewidths using Optical End of Line Metrology (OELM). OELM involves measuring relative line shortening effects that are inherent in many semiconductor fabrication processes using optical overlay instruments. According to one embodiment, the process involves a frame that has two adjacent sides which are constructed of lines and spaces. The frame is imaged onto a wafer, but the optical line measurements used to implement the frame over-predict actual shortening of the lines.

Abstract: Chemical Mechanical Processing (CMP) is widely used for manufacturing semiconductors. CMP is very effective for planarizing geometry that are not widely isolated. One limiting aspect of CMP is that the deposition of the layer being planarized generally has an effective distance over which gaps can be filled. These gaps can fill with a residue that adversely effects the resultant semiconductor. A technique that inhibits the accumulation of residue deposits a sacrificial layer of material after deposition of a planarizing layer, but before CMP. This layer is selected so that it fills the gaps from the manufacturing process, but has little abrasive or solvent resistance. CMP is performed after the sacrificial layer is performed. However, since the gaps are filled, residues cannot collect. Then, after the CMP is performed, the sacrificial layer is removed by applying a solvent to the sacrificial layer. The choice of material for the sacrificial layer is also important.

Abstract: Methods of inspecting for mask-defined, feature dimensional conformity between multiple masks which are utilized in lithographic processing are described. In one embodiment, a first mask having a first reference artifact thereon is exposed to conditions effective to transfer the first reference artifact onto a coated substrate. A second mask having a second reference artifact thereon is exposed to conditions effective to transfer the second reference artifact onto the coated substrate. The first and second reference artifacts are inspected to ascertain whether the second reference artifact is within desirable dimensional tolerances relative to the first reference artifact. In a preferred embodiment, the first and second reference artifacts contain at least one feature which defines a critical dimension of a photolithographic process utilized to form the artifacts.

Abstract: Semiconductor wafer processing methods are described. In one implementation, a semiconductor wafer is provided with a layer of photoresist thereover. A matrix is defined within the photoresist and comprises a plurality of exposed grating patterns which are formed through successive exposure passes of a mask which defines the grating pattern. The wafer is exposed to conditions which are effective to remove at least some of the photoresist and to clear substantially all of the photoresist over a wafer portion underlying at least one of the exposed grating patterns. The wafer is inspected and at least one processing parameter associated with photoresist which was removed during processing can be ascertained. In a preferred aspect, the processing parameter comprises an illumination exposure dosage. In a preferred implementation, two exposure passes with the mask are made with a second of the passes being shifted by a predetermined amount relative to the grating pattern defined by the first pass.

Abstract: The effectiveness of various types of optical proximity correction schemes for avoiding line shortening are easily evaluated by imprinting a test pattern on a semiconductor wafer. The pattern includes an easily measurable standard measurement element not susceptible to line shortening and a test element having a series of parallel lines with narrow widths comparable to the widths of the circuit features that are susceptible to line shortening. The test element also includes the same optical proximity correction scheme whose effectiveness is to be measured. The entire test pattern is photolithographed onto the wafer and the lengths of measurement element and the test element are measured and compared to determine the effectiveness of the correction. Several test patterns, each with a different form of optical proximity correction, can be lithographed onto a single wafer for a comparative review of the different correction schemes both in focus and out of focus both positively and negatively.

Abstract: Line shortening and other defects in integrated circuits are measured by imprinting accuracy determinative patterns in the scribe lines or die margins of the mask field. The patterns are ideally formed in the general nature of the usual box in a box configuration with one of the boxes being specially configured to include a series of lines and spaces having narrow widths comparable to the width of the lines to be formed in the integrated circuit. The use of the narrow lines provides the box in a box configuration with the same line shortening that the circuit feature will itself experience. Small spaces between the lines permit the standard measuring equipment to locate at the ends of the lines.

Abstract: A method for measuring alignment accuracy in a step and repeat system which includes projecting an array of rows and columns of grating features onto a wafer coated with a resist using a first stepping distance and using an increased exposure dosage from row to row of said array; projecting the same array over the first but using a different stepping distance along the rows and also a sufficient offset in the starting positions of the first and second exposures to form a phase difference between the two projection exposures which will result in a complementary alignment of the two exposures at least one column in the array.