Abstract: Aspects of the embodiments are directed to systems, devices, and methods for accessing storage-as-memory. Embodiments include a microprocessor including a microprocessor system agent and a field programmable gate array (FPGA). The FPGA including an FPGA system agent to process memory access requests received from the microprocessor system agent across a communications link; a memory controller communicatively coupled to the system agent; and a high speed serial interface to link the system agent with a storage system. Embodiments can also include a storage device connected to the FPGA by the high speed serial interface.

Abstract: Various methods and systems for autonomously upgrading deployed resources in a distributed computing environment are provided. An autonomous upgrade system identifies updates such as operating system image updates and virtual machine extension updates for deployment in the distributed computing environment. The autonomous upgrade system identifies eligible tenants, identifies deployed resources that may be impacted by the identified update, batches the resources and upgrades the batched resources. The autonomous upgrade system performs a diagnostic test on upgraded resources to determine whether an upgrade was successful. In some embodiments, the diagnostic test is performed by executing a diagnostic script that can be provided by a tenant. The autonomous upgrade system can stop or pause the upgrade if various success metrics are not satisfied. In some embodiments, the autonomous upgrade system tests and certifies newly published updates for deployment to the distributed computing environment.

Abstract: Various methods and systems for implementing an availability management system for implementing an availability management, in distributed computing systems, are provided. An availability management system implements an availability manager and an availability configuration interface to meet availability guarantees for tenant infrastructure. The availability management systems operates with availability zones, computing clusters, fault and upgrade domains to allocate and de-allocate virtual machine sets of virtual machine instances to a distributed computing system based on tenant-defined availability parameters. The availability manager is configured to: based on an availability profile, allocate the virtual machine sets across the availability zones using an allocation scheme.

Abstract: Various methods and systems for implementing an availability management system for implementing an availability management, in distributed computing systems, are provided. An availability management system implements an availability manager and an availability configuration interface to meet availability guarantees for tenant infrastructure. The availability management systems operates with availability zones, computing clusters, fault and upgrade domains to allocate and de-allocate virtual machine sets of virtual machine instances to a distributed computing system based on tenant-defined availability parameters. The availability parameters are used to generate an availability profile. The availability manager is configured to, based on an availability profile, allocate the virtual machine sets based an allocation scheme. The availability manager specifically performs scaling-out, scaling-in and rebalancing operations for allocating and de-allocating the virtual machine sets.

Abstract: Various methods and systems for implementing an availability management system for implementing an availability management, in distributed computing systems, are provided. An availability management system implements an availability manager and an availability configuration interface to meet availability guarantees for tenant infrastructure. The availability management systems operates with availability zones, computing clusters, fault and upgrade domains to allocate and de-allocate virtual machine sets of virtual machine instances to a distributed computing system based on tenant-defined availability parameters. The availability configuration interface of the availability management system supports receiving availability parameters that are used to generate an availability profile.

Abstract: A wireless communication device for collecting vehicle on-board diagnostics (OBD) data is disclosed, together with associated methods of handling OBD data in such wireless communication devices. The device comprises a connector for connecting the device to an OBD port of a vehicle to receive OBD data; a processor configured to continually aggregate the OBD data and/or acceleration data from an acceleration sensor into risk profile data during a journey made by the vehicle; a memory for storing the latest risk profile data for the journey; and a wireless transceiver for transmitting the stored risk profile data to an external mobile device during the journey.

Abstract: Self-repair logic for stacked memory architecture. An embodiment of a memory device includes a memory stack having one or more memory die elements, including a first memory die element, and a system element coupled with the memory stack. The first memory die element includes multiple through silicon vias (TSVs), the TSVs including data TSVs and one or more spare TSVs, and self-repair logic to repair operation of a defective TSV of the plurality of data TSVs, the repair of operation of the defective TSV including utilization of the one or more spare TSVs.

Abstract: A power cylinder system for a reciprocating engine includes a steel piston configured to move within a cylinder of the reciprocating engine. The system also includes a groove extending circumferentially about the piston beneath a top land of the piston and configured to support a ring having an inner circumferential face. One or more channels are formed in the top land and are configured to facilitate transfer of combustion gases to a space between a portion of the groove and the inner circumferential face of the ring.

Abstract: Self-repair logic for stacked memory architecture. An embodiment of a memory device includes a memory stack having one or more memory die elements, including a first memory die element, and a system element coupled with the memory stack. The first memory die element includes multiple through silicon vias (TSVs), the TSVs including data TSVs and one or more spare TSVs, and self-repair logic to repair operation of a defective TSV of the plurality of data TSVs, the repair of operation of the defective TSV including utilization of the one or more spare TSVs.

Abstract: A power cylinder system for a reciprocating engine includes a steel piston configured to move within a cylinder of the reciprocating engine. The system also includes a groove extending circumferentially about the piston beneath a top land of the piston and configured to support a ring having an inner circumferential face. One or more channels are formed in the top land and are configured to facilitate transfer of combustion gases to a space between a portion of the groove and the inner circumferential face of the ring.

Abstract: A built-in self-test for stacked memory architecture. An embodiment of a memory device includes a memory stack including one or more DRAM (dynamic random access memory) elements; and a system element for control of the memory stack. The system element includes a built-in self-test (BIST) engine to generate a write test event or a read test event for the memory stack, a test interface to receive test data for write test event or the read test events from the BIST engine, and a memory controller, the memory control to receive at least a portion of the test data from the test interface and to implement the write test event or read test event at the DRAM elements of the memory stack.

Abstract: Self-repair logic for stacked memory architecture. An embodiment of a memory device includes a memory stack having one or more memory die elements, including a first memory die element, and a system element coupled with the memory stack. The first memory die element includes multiple through silicon vias (TSVs), the TSVs including data TSVs and one or more spare TSVs, and self-repair logic to repair operation of a defective TSV of the plurality of data TSVs, the repair of operation of the defective TSV including utilization of the one or more spare TSVs.

Abstract: A wrappable textile sleeve and method of construction thereof is provided. The sleeve includes a woven wall having opposite inner and outer edges extending in a lengthwise direction along a central longitudinal axis of the sleeve between opposite ends. The opposite inner and outer edges are wrappable into overlapping relation with one another to form an inner tubular cavity. The wall has an innermost woven layer and an outermost woven layer woven in attached relation with one another at one of the opposite inner and outer edges. A reflective layer is sandwiched between the innermost woven layer and the outermost woven layer, such that the outermost woven layer protects the underlying reflective layer against abrasion.

Abstract: A generic address scrambler for a memory circuit test engine. An embodiment of a memory device includes a memory stack having one or more of coupled memory elements, a built-in self-test circuit including a generic programmable address scrambler for the mapping of logical addresses to physical addresses for the memory elements, and one or more registers to hold programming values for the generic programmable address scrambler.

Abstract: A generic data scrambler is provided for a built-in self-test (BIST) engine of a stacked memory device. The stacked memory device includes a memory stack of one or more memory layers; and a system element that is coupled with the memory stack. The system element includes a memory controller for the memory stack; a BIST circuit for testing of the memory stack; and a generic data scrambler for scrambling of data according to a data scrambling algorithm for the memory stack. The generic data scrambler includes a programmable lookup table to hold data factors for each possible outcome of the data scrambling algorithm, and the programmable lookup table is to generate a set of data factors based on addresses of data for testing of the memory stack.

Abstract: Self-repair logic for stacked memory architecture. An embodiment of a memory device includes a memory stack having one or more memory die elements, including a first memory die element, and a system element coupled with the memory stack. The first memory die element includes multiple through silicon vias (TSVs), the TSVs including data TSVs and one or more spare TSVs, and self-repair logic to repair operation of a defective TSV of the plurality of data TSVs, the repair of operation of the defective TSV including utilization of the one or more spare TSVs.

Abstract: In one embodiment the apparatus is a micro-page table engine that includes logic that is capable of receiving a memory page request for a page in global memory address space. The apparatus also includes a translation lookaside buffer (TLB) that is capable of storing one or more memory page address translations. Additionally, the apparatus also has a page miss handler capable of performing a micro physical address lookup in a page miss handler tag table in response to the TLB not storing the memory page address translation for the page of memory referenced by the memory page request. The apparatus also includes memory management logic that is capable of managing the page miss handler tag table entries.

Abstract: A generic address scrambler for a memory circuit test engine. An embodiment of a memory device includes a memory stack having one or more of coupled memory elements, a built-in self-test circuit including a generic programmable address scrambler for the mapping of logical addresses to physical addresses for the memory elements, and one or more registers to hold pro-gramming values for the generic programmable address scrambler.

Abstract: A built-in self-test for stacked memory architecture. An embodiment of a memory device includes a memory stack including one or more DRAM (dynamic random access memory) elements; and a system element for control of the memory stack. The system element includes a built-in self-test (BIST) engine to generate a write test event or a read test event for the memory stack, a test interface to receive test data for write test event or the read test events from the BIST engine, and a memory controller, the memory control to receive at least a portion of the test data from the test interface and to implement the write test event or read test event at the DRAM elements of the memory stack.

Abstract: A generic data scrambler for a memory circuit test engine. An embodiment of a memory device includes a memory; a memory controller for the memory; a built-in self-test (BIST) circuit for the testing of the memory; and a generic data scrambler for scrambling of data according to a scrambling algorithm for the memory, where each algorithm is based on values of an address for data. The generic data scrambler includes a programmable lookup table to hold values for each possible outcome of the algorithm, the lookup table to generate a set of data factors, and a logic for combining the data with the data factors to generate scrambled data.