Abstract: A circuit board assembly having a laminate construction of multiple layers, such as a LTCC ceramic substrate, with conductor lines between adjacent pairs of layers. A heat sink is bonded to a first surface of the substrate, and a cavity is defined by and between the heat sink and the substrate such that a base wall of the cavity is defined by one of the layers with conductor lines thereof being present on the base wall. A surface-mount circuit device is received within the cavity, mounted to the base wall, and electrically connected to the conductor lines on the base wall. The device is received within the cavity such that a surface of the device contacts a surface region of the heat sink. The surface of the device is bonded to the surface region of the heat sink to provide a substantially direct thermal path from the device to the heat sink.

Abstract: In some embodiments, built-in self-test logic is provided for an integrated circuit (IC) device having memory controller logic to generate address and command information for accessing a memory device. Driver circuits are on-chip with the memory controller logic. The driver circuits have outputs that are coupled to on-chip signal pads, respectively. The BIST logic is coupled between the driver circuits and the controller logic. The BIST logic is to transmit, at speed, address and command information that has been generated by the controller logic using the driver circuits in a normal mode of operation for the device. In addition, the BIST logic is able to transmit, at speed, test symbols using the driver circuits in a test mode of operation for the IC device, during which a chip-to-chip connection between the IC device and another device is tested. Other embodiments are also described and claimed.

Abstract: Some embodiments of the invention enable debugging functionality for memory devices residing on a memory module that are buffered from the memory bus by a buffer chip. Some embodiments map connector signals from a tester coupled to the high speed interface between the buffer chip and the memory bus to an interface between the buffer chip and the memory devices. During test mode, some embodiments bypass the normal operational circuitry of the buffer chip and provide a direct connection to the memory devices. Other embodiments use the existing architecture of the buffer chip to convert high speed pins into low speed pins and map them to pins that are connected to the memory devices. Other embodiments are described in the claims.

Abstract: Some embodiments of the invention enable debugging functionality for memory devices residing on a memory module that are buffered from the memory bus by a buffer chip. Some embodiments map connector signals from a tester coupled to the high speed interface between the buffer chip and the memory bus to an interface between the buffer chip and the memory devices. During test mode, some embodiments bypass the normal operational circuitry of the buffer chip and provide a direct connection to the memory devices. Other embodiments use the existing architecture of the buffer chip to convert high speed pins into low speed pins and map them to pins that are connected to the memory devices. Other embodiments are described in the claims.

Abstract: A buffer logic within a memory module having the capability to carry out a test of another memory module to which it is coupled via a point-to-point bus through autonomously storing and transmitting a test pattern across that point-to-point bus to the other memory module, while further employing another buffer logic that is interposed between the two memory modules to pass on the test pattern, but intercept a signal received from the other memory module during the test and pass on an indication of the receipt of that signal to an analysis device to monitor the test.

Abstract: A super-enhanced aquatic floating island plant habitat that is adjustably buoyant and optionally biodegradable. The first embodiment is comprised of a thermoplastic elastomer, a mat, soil/flotation chambers, apertures, nutrient channels, buoyant waterscape options, and a tethering system. The floating island can include monitors that measure water and atmospheric conditions, dispensers for fish food or chemicals, and a water agitation/oxygenation device. Another embodiment comprises a positively buoyant soil matrix contained within a water-permeable bag. Another embodiment comprises a flotation collar, an outrigger, and one or more water-permeable bladders containing negatively or neutrally buoyant bedding soil. The present invention also covers an aquarium-scale floating island and submersible planter, a plant containment bag made out of thermoplastic elastomer, and several methods of adjusting the buoyancy of a floating island.

Abstract: Method and apparatus for use with buffered memory modules are included among the embodiments. In exemplary systems, the memory module has a host-side memory channel port and a downstream memory channel port, allowing multiple modules to be chained point-to-point. In the present disclosure, a separate bus, such as a low-speed system management bus, connects to a memory module buffer. In response to commands received over the system management bus, the memory module can initiate commands and transmit those commands over its downstream memory channel port as if the commands originated from a host connected to the host-side memory channel port. This functionality allows module-to-module memory channels and memory modules to be tested independent of a host memory controller and host memory channel. Other embodiments are described and claimed.

Abstract: An electronic package having enhanced heat dissipation is provided exhibiting dual conductive heat paths in opposing directions. The package includes a substrate and a semiconductor device mounted to the substrate. The semiconductor device has electrical circuitry a first surface, and a second surface oppositely disposed from the first surface. A thermally conductive heat sink is assembled over the semiconductor device such that a cavity is formed between the semiconductor device and the heat sink. A thermally conductive and electrically insulative material is disposed in the cavity between the semiconductor device and the heat sink.

Abstract: An electronic package having enhanced heat dissipation is provided exhibiting dual conductive heat paths in opposing directions. The package includes a substrate having electrical conductors thereon and a flip chip mounted to the substrate. The flip chip has a first surface, solder bumps on the first surface, and a second surface oppositely disposed from the first surface. The flip chip is mounted to the substrate such that the solder bumps are registered with the conductors on the substrate. The package further includes a stamped metal heat sink in heat transfer relationship with the second surface of the flip chip. The heat sink includes a cavity formed adjacent to the flip chip containing a thermally conductive material.

Abstract: In some embodiments, built-in self-test logic is provided for an integrated circuit (IC) device having memory controller logic to generate address and command information for accessing a memory device. Driver circuits are on-chip with the memory controller logic. The driver circuits have outputs that are coupled to on-chip signal pads, respectively. The BIST logic is coupled between the driver circuits and the controller logic. The BIST logic is to transmit, at speed, address and command information that has been generated by the controller logic using the driver circuits in a normal mode of operation for the device. In addition, the BIST logic is able to transmit, at speed, test symbols using the driver circuits in a test mode of operation for the IC device, during which a chip-to-chip connection between the IC device and another device is tested. Other embodiments are also described and claimed.

Abstract: The present invention provides tools and methods of processing microelectronic substrates in which the tools maintain high throughput yet have dramatically lower footprint than conventional tools. In preferred aspects, the present invention provides novel tool designs in which multiple tool functions are overlapped in the x, y, and/or z axes of the tool in novel ways.

Abstract: An apparatus and method of determining remaining capacity in a battery, including the following steps: detecting the presence of a battery within one of a plurality of specified terminals; automatically initiating a timed pulse load test on the battery upon detection in a terminal; continuously passing current from the battery through a specified resistive load for the terminal; measuring a voltage of the battery while under the resistive load; comparing the measured voltage to a discharge voltage profile of the battery; and, computing the measured voltage as a percent of remaining battery capacity.

Abstract: An apparatus and method of determining remaining capacity in a battery, including the following steps: detecting the presence of a battery within one of a plurality of specified terminals; automatically initiating a timed pulse load test on the battery upon detection in a terminal; continuously passing current from the battery through a specified resistive load for the terminal; measuring a voltage of the battery while under the resistive load; comparing the measured voltage to a discharge voltage profile of the battery; and, computing the measured voltage as a percent of remaining battery capacity.

Abstract: A prosthetic device includes an energy storing member, a lever member attached to the energy storing member, a rocking member and an energy transfer line. This line has a first end attached to a front end of the energy storing member and a second end attached to a back end of the lever member. The line has its middle portion attached to the rocking member. The energy storing member is preferably a leaf spring. This combination of elements in the prosthetic device may be a lower leg or foot for use by a below-the-knee amputee to simulate more closely the natural gait of a person while walking or running.

Abstract: A total dose monitor circuit consists of three P-channel MOSFET devices packaged in a CD4007 device and an OP490 bipolar quad operational ampher used to measure and average the sensor outputs. The P-channel transistors in the CD4007 device are used as the total dose sensors in this circuit. MOS transistors are sensitive to total dose degradation and this sensitivity can be exploited in a dose monitoring circuit. The gate threshold voltage, VGS, will shift negatively as a function of total dose exposure due to the trapped charges that build up in the gate interface during ionizing radiation exposure. The threshold voltage shift is directly proportional to the total dose exposure level.

Abstract: This invention relates to an improved process for making titanium dioxide pigment, wherein granular scouring particles (scrubs) comprising specific water-soluble salts (KCl, CsCl, or mixtures thereof) are introduced into a cooling conduit containing a hot gaseous suspension of titanium dioxide particulate. The process provides titanium dioxide pigment having higher carbon black undertone (CBU) levels.