Patents by Inventor Davide Patti

Davide Patti has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8299579
    Abstract: An integrated power transistor includes emitter or source regions, and a comb-like patterned metal electrode structure interconnecting the emitter or source regions and defining at least one connection pad. The comb-like patterned metal electrode structure includes a plurality of fingers. A current sensing resistor produces a voltage drop representative of a current delivered to a load by the integrated power transistor. The current sensing resistor includes a portion of a current carrying metal track having a known resistance value and extending between one of the fingers and a connectable point along the current carrying metal track.
    Type: Grant
    Filed: January 25, 2011
    Date of Patent: October 30, 2012
    Assignee: STMicroelectronics S.R.L.
    Inventors: Davide Patti, Vincenzo Sciacca
  • Publication number: 20110181323
    Abstract: An integrated power transistor includes emitter or source regions, and a comb-like patterned metal electrode structure interconnecting the emitter or source regions and defining at least one connection pad. The comb-like patterned metal electrode structure includes a plurality of fingers. A current sensing resistor produces a voltage drop representative of a current delivered to a load by the integrated power transistor. The current sensing resistor includes a portion of a current carrying metal track having a known resistance value and extending between one of the fingers and a connectable point along the current carrying metal track.
    Type: Application
    Filed: January 25, 2011
    Publication date: July 28, 2011
    Applicant: STMICROELECTRONICS S.R.L.
    Inventors: Davide Patti, Vincenzo Sciacca
  • Patent number: 7911032
    Abstract: An integrated power transistor includes emitter or source regions, and a comb-like patterned metal electrode structure interconnecting the emitter or source regions and defining at least one connection pad. The comb-like patterned metal electrode structure includes a plurality of fingers. A current sensing resistor produces a voltage drop representative of a current delivered to a load by the integrated power transistor. The current sensing resistor includes a portion of a current carrying metal track having a known resistance value and extending between one of the fingers and a connectable point along the current carrying metal track.
    Type: Grant
    Filed: January 4, 2007
    Date of Patent: March 22, 2011
    Assignee: STMicroelectronics S.R.L.
    Inventors: Davide Patti, Vincenzo Sciacca
  • Patent number: 7675135
    Abstract: Instabilities and related drawbacks that arise when interruptions of a perimetral high voltage ring extension implanted regions (RHV) of a main junction (P_tub 1, (P_tub2, . . . ) of an integrated device must be realized may be effectively prevented. This important result is achieved by an extremely simple expedient: whenever an interruption (I) of the high voltage ring extension must be created, it is not realized straight across it along a common orthogonal direction to the perimetral implanted region, on the contrary, the narrow interruption is defined obliquely or slantingly across the width of the perimetral high voltage ring extension. In case of a straight interruption, the angle of slant (?) may be generally comprises between 30 and 60 degrees and more preferably is 45 degrees or close to it. Naturally, the narrow interruption is created by masking it from dopant implantation when realizing the perimetral high voltage ring extension region.
    Type: Grant
    Filed: September 12, 2005
    Date of Patent: March 9, 2010
    Assignee: STMicroelectronics S.R.L.
    Inventors: Davide Patti, Giuditta Settanni
  • Patent number: 7528461
    Abstract: A bipolar power transistor does not include integration of a Zener diode electrically connected between the base and collector for limiting the collector voltage. The power transistor is formed in a substrate, and includes an equalization diffusion and an auxiliary diffusion forming a P-N junction along a perimeter of the substrate. An equalization conduction layer is in contact with the equalization diffusion and the auxiliary diffusion for electrically shorting the P-N junction.
    Type: Grant
    Filed: June 9, 2006
    Date of Patent: May 5, 2009
    Assignee: STMicroelectronics S.r.l.
    Inventors: Davide Patti, Sebastiano Aparo
  • Publication number: 20080237773
    Abstract: Instabilities and related drawbacks that arise when interruptions of a perimetral high voltage ring extension implanted regions (RHV) of a main junction (P_tub 1, (P_tub2, . . . ) of an integrated device must be realized may be effectively prevented. This important result is achieved by an extremely simple expedient: whenever an interruption (I) of the high voltage ring extension must be created, it is not realized straight across it along a common orthogonal direction to the perimetral implanted region, on the contrary, the narrow interruption is defined obliquely or slantingly across the width of the perimetral high voltage ring extension. In case of a straight interruption, the angle of slant (?) may be generally comprises between 30 and 60 degrees and more preferably is 45 degrees or close to it. Naturally, the narrow interruption is created by masking it from dopant implantation when realizing the perimetral high voltage ring extension region.
    Type: Application
    Filed: September 12, 2005
    Publication date: October 2, 2008
    Inventors: Davide Patti, Giuditta Settanni
  • Publication number: 20070194828
    Abstract: An integrated power transistor includes emitter or source regions, and a comb-like patterned metal electrode structure interconnecting the emitter or source regions and defining at least one connection pad. The comb-like patterned metal electrode structure includes a plurality of fingers. A current sensing resistor produces a voltage drop representative of a current delivered to a load by the integrated power transistor. The current sensing resistor includes a portion of a current carrying metal track having a known resistance value and extending between one of the fingers and a connectable point along the current carrying metal track.
    Type: Application
    Filed: January 4, 2007
    Publication date: August 23, 2007
    Applicant: STMicroelectronics S.r.l.
    Inventors: Davide Patti, Vincenzo Sciacca
  • Publication number: 20070024118
    Abstract: A power IGBT device is monolithically integrated to include an input terminal suitable to receive an input voltage and an output terminal suitable to supply a current having a limited and predetermined highest value. Such IGBT device includes an IGBT power element inserted between said output terminal and a supply reference. The power element has a control terminal connected to the input terminal through a control circuit that includes at least a transistor inserted between the control terminal and the supply reference voltage and a resistive element inserted between the input terminal and the control terminal.
    Type: Application
    Filed: May 22, 2006
    Publication date: February 1, 2007
    Applicant: STMicroelectronics S.r.l.
    Inventors: Antonino Torres, Stefano Sueri, Davide Patti
  • Publication number: 20070013032
    Abstract: A bipolar power transistor does not include integration of a Zener diode electrically connected between the base and collector for limiting the collector voltage. The power transistor is formed in a substrate, and includes an equalization diffusion and an auxiliary diffusion forming a P-N junction along a perimeter of the substrate An equalization conduction layer is in contact with the equalization diffusion and the auxiliary diffusion for electrically shorting the P-N junction.
    Type: Application
    Filed: June 9, 2006
    Publication date: January 18, 2007
    Applicant: STMicroelectronics S.r.l.
    Inventors: Davide Patti, Sebastiano Aparo
  • Patent number: 7126167
    Abstract: A device integrated in a semiconductor substrate of a first type of conductivity being crowned by a semiconductor layer of a second type of conductivity comprising a voltage controlled resistive structure and an IGBT device, wherein the resistive structure comprises at least one substantially annular region of the first type of conductivity which surrounds a portion of the semiconductor layer.
    Type: Grant
    Filed: July 9, 2004
    Date of Patent: October 24, 2006
    Assignee: STMicroelectronics S.r.l.
    Inventors: Davide Patti, Antonino Torres
  • Patent number: 7053463
    Abstract: The manufacturing process comprises the steps of growing epitaxially a first layer from a semiconductor material substrate, forming in the first layer a first and a second buried region spaced from one another and having conductivity of the type opposite that of the first layer; growing epitaxially on the first layer a second layer of semiconductor material having the same type of conductivity as the first layer; forming in the second layer a trench extending in depth beyond the buried regions, arranged between the buried regions, and having, in plan view, a frame shape; forming an oxide layer covering the lateral walls and the base wall of the trench; and filling the remaining part of the trench with an isolating material.
    Type: Grant
    Filed: January 12, 2004
    Date of Patent: May 30, 2006
    Assignee: STMicroelectronics S.r.l.
    Inventor: Davide Patti
  • Publication number: 20050184793
    Abstract: A circuit for dynamic control of a power transistor in applications for high voltage and of the type wherein a power transistor has a conduction terminal connected to a load and a control terminal receiving a driving signal from a driver block activated by a trigger signal received on a circuit input terminal. Advantageously, the circuit comprises a JFET component inserted between the conduction and control terminal of the power transistor and equal to a resistance with a non-linear feature. Moreover, the JFET component may be monolithically integrated in the structure of said power transistor.
    Type: Application
    Filed: January 24, 2005
    Publication date: August 25, 2005
    Inventors: Antonino Torres, Davide Patti
  • Publication number: 20050051813
    Abstract: A device integrated in a semiconductor substrate of a first type of conductivity being crowned by a semiconductor layer of a second type of conductivity comprising a voltage controlled resistive structure and an IGBT device, wherein the resistive structure comprises at least one substantially annular region of the first type of conductivity which surrounds a portion of the semiconductor layer.
    Type: Application
    Filed: July 9, 2004
    Publication date: March 10, 2005
    Applicant: STMicroelectronics S.r.l.
    Inventors: Davide Patti, Antonino Torres
  • Patent number: 6815798
    Abstract: A capacitor for sensing a substrate voltage in an integrated circuit power device may be implemented by isolating a portion or segment of the metal layer that normally covers the heavily doped perimeter region typically used for electric field equalization. In conjunction, one or more portions of an isolation dielectric layer of silicon oxide are not removed from the surface of the semiconductor substrate, as is commonly done before depositing the metal layer. The portions of isolated silicon oxide which are not removed become the dielectric layer of the capacitor. Moreover, one plate of the capacitor is formed by the heavily doped perimeter region that is electrically connected to the substrate (e.g. a drain or collector region). The other plate is formed by the segment of metal isolated from the remaining metal layer defined directly over the heavily doped perimeter region.
    Type: Grant
    Filed: May 15, 2003
    Date of Patent: November 9, 2004
    Assignee: STMicronelectronics S.r.l.
    Inventors: Natale Aiello, Davide Patti
  • Publication number: 20040183158
    Abstract: The manufacturing process comprises the steps of growing epitaxially a first layer from a semiconductor material substrate, forming in the first layer a first and a second buried region spaced from one another and having conductivity of the type opposite that of the first layer; growing epitaxially on the first layer a second layer of semiconductor material having the same type of conductivity as the first layer; forming in the second layer a trench extending in depth beyond the buried regions, arranged between the buried regions, and having, in plan view, a frame shape; forming an oxide layer covering the lateral walls and the base wall of the trench; and filling the remaining part of the trench with an isolating material.
    Type: Application
    Filed: January 12, 2004
    Publication date: September 23, 2004
    Applicant: STMicroelectronics S.r.l.
    Inventor: Davide Patti
  • Publication number: 20040178474
    Abstract: A lateral-current-flow integrated transistor, formed in an epitaxial layer defining a base well with a first conductivity type, which accommodates emitter and collector regions of a second conductivity type. The collector region is formed by an internal conductive region and by an external conductive region, and the emitter region is formed by an intermediate conductive region. The external conductive region has an annular shape and surrounds the intermediate conductive region, which also has an annular shape and surrounds the internal conductive region.
    Type: Application
    Filed: December 12, 2003
    Publication date: September 16, 2004
    Applicant: STMicroelectronics S.r.l.
    Inventor: Davide Patti
  • Patent number: 6774061
    Abstract: A process for forming a thin layer of Silicon nanocrystals in an oxide layer is disclosed. The process includes, on a semiconductive substrate, thermally oxidizing a first portion of the substrate into an oxide layer, forming Silicon ions within the layer of oxide, and thermally treating the Silicon ions to become the thin layer of Silicon nanocrystals. In the inventive process the formation of the Silicon ions is by ionic implantation of the Silicon ions into the oxide at an ionization energy of between 0.1 keV and 7 keV, and preferably between 1 and 5 keV. This allows the Silicon atoms to coalesce in a lower temperature than would otherwise be possible. Additionally, more than one layer of nanocrystals can be formed by performing more than one implantation at more than one energy level. Embodiments of the invention can be used to form non-volatile memory devices with a very high quality having a very small size.
    Type: Grant
    Filed: March 15, 2001
    Date of Patent: August 10, 2004
    Assignee: STMicroelectronics S.r.l.
    Inventors: Salvatore Coffa, Davide Patti
  • Patent number: 6696916
    Abstract: The high-voltage resistor is of the vertical type, and is formed in a chip which includes a high-voltage region and a low-voltage region superimposed on the high-voltage region, both having a first conductivity type. An isolation region, at least partially buried, extends between the high-voltage region and the low-voltage region, and delimits a vertical resistive region connecting the high-voltage region to the low-voltage region.
    Type: Grant
    Filed: December 22, 2000
    Date of Patent: February 24, 2004
    Assignee: STMicroelectronics S.r.l.
    Inventors: Delfo Sanfilippo, Davide Patti
  • Patent number: 6696741
    Abstract: PN junction structure including a first junction region of a first conductivity type, and a second junction region of a second conductivity type, wherein between said first and second junction regions a grid of buried insulating material regions is provided.
    Type: Grant
    Filed: November 19, 1999
    Date of Patent: February 24, 2004
    Assignee: STMicroelectronics S.r.l.
    Inventors: Cesare Ronsisvalle, Piero Giorgio Fallica, Davide Patti
  • Publication number: 20040016960
    Abstract: A capacitor for sensing a substrate voltage in an integrated circuit power device may be implemented by isolating a portion or segment of the metal layer that normally covers the heavily doped perimeter region typically used for electric field equalization. In conjunction, one or more portions of an isolation dielectric layer of silicon oxide are not removed from the surface of the semiconductor substrate, as is commonly done before depositing the metal layer. The portions of isolated silicon oxide which are not removed become the dielectric layer of the capacitor. Moreover, one plate of the capacitor is formed by the heavily doped perimeter region that is electrically connected to the substrate (e.g. a drain or collector region). The other plate is formed by the segment of metal isolated from the remaining metal layer defined directly over the heavily doped perimeter region.
    Type: Application
    Filed: May 15, 2003
    Publication date: January 29, 2004
    Applicant: STMicroelectronics S.r.l.
    Inventors: Natale Aiello, Davide Patti