Abstract: An electronic device, integrated monolithically in a semiconductor substrate and comprising a bipolar transistor connected in series to at least one MOS transistor, the bipolar transistor having a base region that includes a first buried region and a first diffused region extending continuously from the substrate surface down to the buried region, and the diffused region is bordered by an isolation trench region extending in the buried region.

Abstract: A structure for a semiconductor resistive element, applicable in particular to power components, having a high concentration substrate of the n type, a first epitaxial layer of the n type, a region of the p type arranged on said first epitaxial layer so to form the resistive element proper, a second epitaxial layer of n type grown on said first epitaxial layer to make the region of the p type a buried region, and an additional layer of the n type with a higher concentration with respect to the second epitaxial level, positioned on the embedded region. Low resistivity regions of the p type adapted to make low resistivity deep contacts for the resistor are provided. The buried region can be made either with a development that is substantially uniform in its main direction of extension or so to present, at on part of its length, a structure of adjacent subregions in marginal continuity.

Abstract: The lateral DMOS transistor is integratable in a semiconductor power device comprising a P-type substrate and an N-type epitaxial layer. The lateral DMOS transistor comprises a source region and a drain region formed in the epitaxial layer and a body region housing the source region. Between the source region and the drain region is present an insulating region extending in depth from a top surface of the epitaxial layer as far as the substrate. The insulating region presents an interruption in a longitudinal direction defining a channeling region for a current ID flowing between the source region and the drain region of the lateral DMOS transistor.

Abstract: A power semiconductor device structure formed in a chip of semiconductor material includes an N-type substrate and an N-type epitaxial layer. The structure comprises a P-type insulation region which forms a pocket in which control circuitry is formed, and a plurality of fully insulated PNP power transistors. Each PNP power transistor comprises a P-type collector region including of a buried region between the substrate and the epitaxial layer and a contact region. The P region delimits a base N region within which an emitter P region is formed.

Abstract: An electronic power device is integrated on a semiconductor substrate having a first conductivity type, on which an epitaxial layer of the same conductivity type is grown. The power device comprises a power stage and a control stage, this latter enclosed in an isolated region having a second conductivity type. The power stage comprises a first buried area having the second conductivity type and a second buried area, partially overlapping the first buried area and having the first conductivity type. The control stage comprises a third buried area, having the second conductivity type, and a fourth buried area, partially overlapped to the third buried area and having the first conductivity type. Said first, second, third and fourth buried areas are formed in the epitaxial layers at a depth sufficient to allow the power stage and the control stage to be entirely formed in the epitaxial layer.

Abstract: A chip of semiconductor material includes a first layer with a first type of conductivity having a surface on the first major surface of the chip, a second layer with the first type of conductivity having a surface on the second major surface of the chip, and a third layer with the first type of conductivity having a resistivity lower than those of the first and second layers and disposed between the first layer and the second layer. A first region with a second, type of conductivity, extends from the first surface into the first layer, and a second region with the second type of conductivity, extends from the second major surface into the second layer. First, second and third electrical connections are provided for connection with the first region, the second region, and the third layer, respectively.

Abstract: An electronic power device is integrated on a substrate of semiconductor material having a first conductivity type, on which an epitaxial layer of the same type of conductivity is grown. The power device comprises a power stage PT and a control stage CT, this latter enclosed in an isolated region having a second type of conductivity type. The power stage PT comprises a first buried area having the second type of conductivity type and a second buried area, partially overlapping the first buried area and having the first conductivity type. The isolation region and the control stage CT comprise respectively a third buried area, having the second conductivity type, and a fourth buried area, partially overlapped to the third buried area and having the first conductivity type. Said first, second, third and fourth buried areas are formed in the epitaxial layers at a depth sufficient to allow the power stage PT and the control stage CT to be entirely formed in the epitaxial layers.

Abstract: The integrated circuit device has a vertical conduction structure in which a region, which contains the base of a bipolar transistor, has zones having different concentrations. The concentrations are lower where the flow of charges is more intense and higher elsewhere. A high gain of the bipolar transistor and a low resistance of the electronic switch in conduction are thus obtained.

Abstract: The device is constituted by an N+ substrate, by an N− layer on the substrate, by a metal contact for a collector, by a buried P− base region, by a P+ base contact and insulation region within which an insulated N region is defined, by a metal contact on the base contact region for a base, by an N+ emitter region buried in the insulated region and forming a pn junction with the buried base region, by a P+ body region in the insulated region, by an N+ source region in the P+ region, by a metal contact for a source, and by a gate electrode. In order to achieve a low resistance Ron, the P+ body region extends as far as the buried N+ emitter region and an additional N+ region is provided within the body region and constitutes a drain region, defining, with the source region, the channel of a lateral MOSFET transistor.

Abstract: The lateral DMOS transistor is integratable in a semiconductor power device comprising a P-type substrate and an N-type epitaxial layer. The lateral DMOS transistor comprises a source region and a drain region formed in the epitaxial layer and a body region housing the source region. Between the source region and the drain region is present an insulating region extending in depth from a top surface of the epitaxial layer as far as the substrate. The insulating region presents an interruption in a longitudinal direction defining a channeling region for a current ID flowing between the source region and the drain region of the lateral DMOS transistor.

Abstract: A structure for a semiconductor resistive element, applicable in particular to power components, having a high concentration substrate of the n type, a first epitaxial layer of the n type, a region of the p type arranged on said first epitaxial layer so to form the resistive element proper, a second epitaxial layer of n type grown on said first epitaxial layer to make the region of the p type a buried region, and an additional layer of the n type with a higher concentration with respect to the second epitaxial level, positioned on the embedded region. Low resistivity regions of the p type adapted to make low resistivity deep contacts for the resistor are provided. The buried region can be made either with a development that is substantially uniform in its main direction of extension or so to present, at on part of its length, a structure of adjacent subregions in marginal continuity.

Abstract: The high-voltage resistor is of the vertical type, and is formed in a chip which includes a high-voltage region and a low-voltage region superimposed on the high-voltage region, both having a first conductivity type. An isolation region, at least partially buried, extends between the high-voltage region and the low-voltage region, and delimits a vertical resistive region connecting the high-voltage region to the low-voltage region.

Abstract: A submicrometer vertical-channel MOSFET of high quality and reproducibility is produced by a method compatible with DPSA technology. The method steps are performed on a wafer of semiconductor material having a layer with n conductivity. First, n impurity ions and p impurity ions are implanted in an area of the layer and the wafer is subjected to a high-temperature treatment. The impurities, the implantation doses and energies, and the high-temperature treatment time and temperature being such as to form a first p region, and a second n region which forms a pn junction with the first region. A trench is hollowed out which intersects the first region and the second regions.

Abstract: A process for forming a thin layer of Silicon nanocrystals in an oxide layer is disclosed. The process includes, on a semiconductive substrate, thermally oxidizing a first portion of the substrate into an oxide layer, forming Silicon ions within the layer of oxide, and thermally treating the Silicon ions to become the thin layer of Silicon nanocrystals. In the inventive process the formation of the Silicon ions is by ionic implantation of the Silicon ions into the oxide at an ionization energy of between 0.1 keV and 7 keV, and preferably between 1 and 5 keV. This allows the Silicon atoms to coalesce in a lower temperature than would otherwise be possible. Additionally, more than one layer of nanocrystals can be formed by performing more than one implantation at more than one energy level. Embodiments of the invention can be used to form non-volatile memory devices with a very high quality having a very small size.

Abstract: A process for manufacturing deep well junction structures that includes in succession, the steps of: on a first substrate having a first conductivity type and a first doping level, growing an epitaxial layer having the first conductivity type and a second doping level lower than the first doping level; anisotropically etching the epitaxial layer using a mask to form trenches; forming deep conductive regions surrounding the trenches and having a second conductivity type, opposite to the first conductivity type and the second doping level; and filling the trenches. The deep conductive regions are formed by angular ionic implantation and subsequent diffusion of a doping ion species within the epitaxial layer.

Abstract: An electronic device, integrated monolithically in a semiconductor substrate and comprising a bipolar transistor connected in series to at least one MOS transistor, the bipolar transistor having a base region that includes a first buried region and a first diffused region extending continuously from the substrate surface down to the buried region, and the diffused region is bordered by an isolation trench region extending in the buried region.

Abstract: A transistor including an epitaxial layer with a first conductivity type, a base buried region with a second conductivity type, and a sinker base region with the second conductivity type which extends from a main surface of the transistor to the base buried region, and delimits, together with the base buried region, emitter fingers in the epitaxial layer. The transistor further includes an emitter buried region with the first conductivity type and a doping level which is higher than that of the epitaxial layer. The emitter buried region is embedded in the epitaxial layer in a position adjacent to the base buried region. A sinker emitter region having the first conductivity type and a doping level which is higher than that of the epitaxial layer and extends from the main surface to the emitter buried region inside the emitter fingers.

Abstract: The manufacturing process comprises the steps of growing epitaxially a first layer from a semiconductor material substrate, forming in the first layer a first and a second buried region spaced from one another and having conductivity of the type opposite that of the first layer; growing epitaxially on the first layer a second layer of semiconductor material having the same type of conductivity as the first layer; forming in the second layer a trench extending in depth beyond the buried regions, arranged between the buried regions, and having, in plan view, a frame shape; forming an oxide layer covering the lateral walls and the base wall of the trench; and filling the remaining part of the trench with an isolating material.

Abstract: A transistor including an epitaxial layer with a first conductivity type, a base buried region with a second conductivity type, and a sinker base region with the second conductivity type which extends from a main surface of the transistor to the base buried region, and delimits, together with the base buried region, emitter fingers in the epitaxial layer. The transistor further includes an emitter buried region with the first conductivity type and a doping level which is higher than that of the epitaxial layer. The emitter buried region is embedded in the epitaxial layer in a position adjacent to the base buried region. A sinker emitter region having the first conductivity type and a doping level which is higher than that of the epitaxial layer and extends from the main surface to the emitter buried region inside the emitter fingers.

Abstract: A bipolar power transistor of interdigitated geometry having a buried P type base region, a buried N type emitter region, a P type base-contact region, an N type emitter-contact region, connected to an emitter electrode and an N type connection region disposed around the emitter-contact region. The emitter region is buried within the base region in such a way that the buried emitter region and the connection region delimit a P type screen region. The transistor further includes a biasing P type region in contact with the emitter electrode, which extends up to the screen region.