Abstract: The present invention achieves technical advantages as an improved Parallel Damping scheme suitable for very-low-supply preamp operation. The improved Parallel Damping Scheme accurately generates a programmable Iw flowing through the write head while compensating for a leakage current path through a Parallel Damping resistor.

Abstract: An amplifier (70) has a differential input stage (84,86). An output transistor (102) is connected to receive a single ended output developed by transistor 86. First (74) and second (76) current sources are connected to establish respective first and second currents in the input differential transistors (84,86) according to a predetermined ratio. First and second voltages are subtracted from the differential inputs (VM,VP) in respective differential amplifiers (88,90), and the output is derived from the output transistor having a magnitude proportional to an inverse of a product of a square of the reference resistance, a carrier mobility, and an oxide capacitance.

Abstract: An apparatus configured according to characteristics for driving a write head to write to a memory device includes: (a) a current directing circuit directing a write current through a first circuit path or a second including the write head in response to a first or second write signal; (b) at least one of: (1) an impedance system for including at least one impedance unit within each of the first and second current paths; and (2) a current system for including at least one circuit element between a locus at each end of said write head and a supply voltage; and (c) a control unit coupled with at least one of the impedance system and the current system for effecting the including for at least one of the impedance system and the current system to effect configuring the apparatus.

Abstract: An apparatus configured according to characteristics for driving a write head to write to a memory device includes: (a) a current directing circuit directing a write current through a first circuit path or a second including the write head in response to a first or second write signal; (b) at least one of: (1) an impedance system for including at least one impedance unit within each of the first and second current paths; and (2) a current system for including at least one circuit element between a locus at each end of said write head and a supply voltage; and (c) a control unit coupled with at least one of the impedance system and the current system for effecting the including for at least one of the impedance system and the current system to effect configuring the apparatus.

Abstract: A method for affecting speed of transition of a closed loop circuit from an initial state to a steady state during a transition period; the closed loop circuit including a switching unit effecting the transition in response to a gating signal applied to a gate locus at a value greater than a predetermined threshold potential; includes the steps of: (a) at least one of: (1) clamping the gate locus at a minimum potential greater than ground potential and less than the predetermined threshold potential; and (2) increasing potential at the gate locus at a plurality of various rates during a plurality of segments of the transition period.

Abstract: An amplifier (70) has a differential input stage (84,86). An output transistor (102) is connected to receive a single ended output developed by transistor 86. First (74) and second (76) current sources are connected to establish respective first and second currents in the input differential transistors (84,86) according to a predetermined ratio. First and second voltages are subtracted from the differential inputs (VM,VP) in respective differential amplifiers (88,90), and the output is derived from the output transistor having a magnitude proportional to an inverse of a product of a square of the reference resistance, a carrier mobility, and an oxide capacitance.

Abstract: An MR head bias circuit (60) in a preamplifier includes a balanced driving circuit (62,64) for connection to the MR head (12) at respective first (66) and second (68) output nodes and impedance matching elements (72,74) to match an output impedance at each output node (66,68) to each other. The impedance matching elements (72,74) may match an output impedance at each output node (66,68) to make them substantially the same.

Abstract: A mass data storage device system (70) and method for providing frequency compensation within it are disclosed. The system has a moving media (72) that contains signals encoded in oriented magnetic domains that are detected by a magneto-resistive head (78) positioned in proximity thereto. An amplifier stage (100 or 120) is connected to sense the change in the electrical characteristic of the head, and capacitors (102-105 or 126-131) are operatively connected within the amplifier stage to produce two or three poles in a frequency response of the amplifier stage to reduce a second order frequency response of the head. Preferably, the poles have substantially identical pole locations.

Abstract: A preamplifier system includes an amplifier stage having at least one feedback network. The feedback network has a feedback resistance that may be adjusted to improve a frequency response of the preamplifier. A feedback control system is operative to set the resistance of the feedback network as a function of a resistance value of an associated read/write head.

Abstract: A preamplifier system includes an amplifier stage having at least one feedback network. The feedback network has a feedback resistance that may be adjusted to improve a frequency response of the preamplifier. A feedback control system is operative to set the resistance of the feedback network as a function of a resistance value of an associated read/write head.

Abstract: Preamplifiers are used in hard disk drive applications to read data stored on magnetic disk. Current bias current sense preamplifiers have a problem with bandwidth rolloff due to relatively high inductance. Voltage sense preamplifiers have a problem with peaking due to input capacitance. An improved current bias voltage sense preamplifier inserts a PMOS transistor M3 between the Rmr head and the bipolar transistor Q0. The PMOS transistor M3 and the bipolar transistor Q0 form a high impedance voltage sense preamplifier. Biasing of the MR head is performed transistors M6 and M7 that mirror the current supplied by the current digital to analog converter into the MR head. Hence, the preamplifier is also of the current bias type. Peaking is controlled through a programmable current in an input capacitance cancellation circuit 30.

Abstract: A voltage to current conversion circuit is described. The circuit comprises a first differential amplifier for receiving an input voltage and producing an output voltage, and a second amplifier for converting the output voltage of the first amplifier to a current. The transfer function of the voltage to current conversion circuit is proportional to an exponential function that depends on the input voltage. The circuit is temperature and process independent. In a first preferred embodiment, the first amplifier comprises a first transistor for receiving an input voltage at its base terminal, a temperature dependent current source coupled to the emitter of the first transistor, and a positive voltage supply coupled to the collector through a diode coupled transistor, and a second transistor paired with the first transistor and having a base terminal coupled to an input voltage terminal, an emitter coupled to a temperature dependent current source, and a collector coupled to a voltage supply.

Abstract: A circuit is designed with a first transconductor circuit (903) with a first input terminal (901) coupled to receive a voltage signal, a second input terminal (1017) coupled to receive a control signal and an output terminal. The first transconductor circuit has a gain responsive to the control signal. A first integrator circuit (905) has an input terminal coupled to the first transconductor circuit output terminal and has an output terminal. A second transconductor circuit (909) has an input terminal coupled to the first integrator circuit output terminal and an output terminal. A second integrator circuit (911) has an input terminal coupled to the second transconductor circuit output terminal and has an output terminal.

Abstract: A hard disk drive system (10) includes a read/write head (21) for reading and writing data to and from a rotating magnetic disk (12). The read/write head includes a portion which is a magneto-resistive read head (36), the output of which is supplied through a preamplifier (26) to a read channel circuit (27). The read head has a nonlinear transfer function. The read channel circuit includes an asymmetry compensation circuit (62), which generates an analog compensation signal by squaring an output signal from the read head and scaling by an asymmetry factor (.alpha.'). The analog compensation signal is combined with the analog output signal in order to obtain a corrected analog signal, which is substantially free of the distortion introduced by the read head.

Abstract: A method for generating a response in a transconductance circuit includes receiving a circuit differential voltage input and providing a differential voltage input to each of a plurality of differential pairs to control, in part, a differential current generated by each differential pair. Each differential voltage input has a different common-mode voltage level. The method also includes sinking current through each of the differential pairs to control the differential current generated by each differential pair. The magnitude of the current sunk through one of the differential pairs is different from the magnitude of the current sunk through at least one of the other differential pairs. The method also includes combining the generated differential current from each of the plurality of differential pairs to produce a differential current output.

Abstract: A read channel (18) for use in a mass storage system is provided. The read channel (18) includes a plurality of circuit modules circuit and an error estimation circuit (50). The plurality of circuit modules may include circuitry such as a VGA (40), an LPF (42), and an equalizer (48), for conditioning an analog data signal. The plurality of circuit modules receive the analog data signal from a disk/head assembly (12) and condition the signal to generate a digital data signal. The error estimation circuit (50) receives an analog signal from one of the plurality of circuit modules, such as the equalizer (48), and analyzes the analog signal to generate an analog error output signal (94) that is used in the read channel (18) and provided to external circuitry.

Abstract: A programmably variable transconductance circuit (10) and method for varying its transconductance includes first and second current control input devices (16, 18), each having an input (17,19) to which a differential input voltage may be applied. A pair of current steering circuits (26, 28, 30, 32) are each connected in series with a respective one of the first and second current control devices (16, 18) for dividing respective currents in the first and second current control devices (16, 18) between a differential output current path (12, 14) and another current flow path, and a programmable voltage source (90) supplying V.sub.CONTROL is connected to control the current division by the current steering circuits (26, 28, 30, 32). The programmable voltage, V.sub.CONTROL, is provided by a programmable current control loop (90), which incorporates a master transconductance circuit, to establish a constant transconductance independently of temperature variations.

Abstract: An exponentiator circuit (24) is provided that includes a first transistor device, that includes a BJT (80) and a BJT (84) configured in a Darlington configuration, and a second transistor device that includes a BJT (88) and a BJT (92) also configured in a Darlington configuration. The first transistor device is coupled between a reference voltage and a summing node, while the second transistor device is coupled between an output node and a summing node. A programmable current iI is provided to the first transistor device and the second transistor device such that the base-to-emitter voltages of the two devices are provided at a different level. This results in the generation of a first current through the first transistor device and an output current through the second transistor device. An input current is provided at the summing node which is equivalent to the sum of the first current and the output current. The overall gain of the exponentiator circuit (24) is approximately exponential.

Abstract: A method and circuit for generating an updated metric signal for an analog Viterbi detector is disclosed.

Abstract: An improved power-up circuit utilizing a simple current channel to rapidly charge or discharge nodes during the power-up transient, the time from when the circuit is signaled to power up to the time when the circuit becomes fully functional. The invention allows critical nodes previously limiting the power-up sequence to be rapidly charged to significantly improve the power-up performance of power savings circuits.