Abstract: A write data precompensator system is described which comprises a delay element circuit (12) which receives a clock signal and outputs a delayed clock signal which includes a programmable selectable delay in the rising edge of the clock signal. The amount of delay is received using a delay voltage level generated by a delay level circuit (16) which receives delay magnitude control values in digital form. A reference level circuit (18) also generates a continuous level voltage level so that the delay element circuit (12) can instantly change between a delayed operation and an undelayed operation without waiting for the delay voltage level to adjust.

Abstract: A logic gate with highly matched output rise and fall times is provided which includes at least one stacked transistor pair (24) and at least one complementary stacked transistor pair (30) connected in parallel across at least one node (NODE 1 and NODE 2).

Abstract: A source of equally spaced timing signals which includes a first signal source providing a first signal tracing an essentially exponential voltage curve, a second signal source including a transistor having a control electrode and an electron flow path therethrough having a voltage drop V.sub.BE thereacross, a voltage source providing a voltage V.sub.CC coupled to one end of the electron flow path, a resistance R.sub.L coupled between the control electrode and the voltage source, the other end of the flow path providing a second voltage signal in accordance with the equation V.sub.i =V.sub.H -I.sub.i R.sub.L for i=1 to n where I.sub.i =(V.sub.H /R.sub.L)(1-e.sup.-i.alpha.) and V.sub.H =V.sub.CC -V.sub.BE and a comparator providing a timing signal whenever the second voltage signal is greater than the first signal.

Abstract: A rectangular-to-sine wave converter circuit (10) is provided that comprises a flip-flop (12) that provides for a square wave and an inverse square wave circuit with fifty percent duty cycles. Each of the square wave signals is passed through a multi-stage low pass filter. The stages of the low pass filters are separated by buffers (26) and (32). The common mode voltage of the output signals at output nodes (40) and (44) are adjusted with respect to an arbitrary bias voltage V.sub.bias by using bias resistors (42) and (68).