Patents by Inventor Daxiang Wang

Daxiang Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10553488
    Abstract: Devices and methods for forming a device are disclosed. The method includes providing a substrate having first and second surfaces. At least one through silicon via (TSV) opening is formed in the substrate. The TSV opening extends through the first and second surfaces of the substrate. An alignment trench corresponding to an alignment mark is formed in the substrate. The alignment trench extends from the first surface of the substrate to a depth shallower than a depth of the TSV opening. A dielectric liner layer is provided over the substrate. The dielectric liner layer at least lines sidewalls of the TSV opening. A conductive layer is provided over the substrate. The conductive layer fills at least the TSV opening to form TSV contact. A redistribution layer (RDL) is formed over the substrate. The RDL layer is patterned using a reticle to form at least one opening which corresponds to a TSV contact pad. The reticle is aligned using the alignment mark in the substrate.
    Type: Grant
    Filed: September 21, 2017
    Date of Patent: February 4, 2020
    Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.
    Inventors: Shunqiang Gong, Juan Boon Tan, Shijie Wang, Mahesh Bhatkar, Daxiang Wang
  • Patent number: 10221360
    Abstract: A method for Fischer-Tropsch synthesis, the method including: 1) gasifying a raw material to obtain a crude syngas including H2, CO and CO2; 2) electrolyzing a saturated NaCl solution using a chloralkali process to obtain a NaOH solution, Cl2 and H2; 3) removing the CO2 in the crude syngas using the NaOH solution obtained in 2) to obtain a pure syngas; and 4) insufflating the H2 obtained in 2) to the pure syngas to adjust a mole ratio of CO/H2 in the pure syngas, and then introducing the pure syngas for Fischer-Tropsch synthesis reaction. A device for Fischer-Tropsch synthesis includes a gasification device, an electrolyzer, a first gas washing device, and a Fischer-Tropsch synthesis reactor.
    Type: Grant
    Filed: December 4, 2017
    Date of Patent: March 5, 2019
    Assignee: WUHAN KAIDI ENGINEERING TECHNOLOGY RESEARCH INSTITUTE CO., LTD.
    Inventors: Daxiang Wang, Pingyu Kuai, Meng Li, Yanfeng Zhang
  • Patent number: 10199572
    Abstract: Device and methods of forming a device are disclosed. The method includes providing a substrate defined with at least first and second regions. A first dielectric layer is provided over the first and second regions of the substrate. The first dielectric layer corresponds to pre-metal dielectric (PMD) or CA level which comprises a plurality of contact plugs in the first and second regions. A first interlevel dielectric (ILD) layer is provided over the first dielectric layer. The first ILD layer accommodates a plurality of metal lines in M1 metal level in the first and second regions and via contact in V0 via level in the first region. A magnetic random access memory (MRAM) cell is formed in the second region. The MRAM cell includes a magnetic tunnel junction (MTJ) element sandwiched between the M1 metal level and CA level.
    Type: Grant
    Filed: May 26, 2016
    Date of Patent: February 5, 2019
    Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.
    Inventors: Wanbing Yi, Yi Jiang, Daxiang Wang, Wei Shao, Juan Boon Tan
  • Patent number: 10121964
    Abstract: Integrating magnetic random access memory with logic is disclosed. The magnetic tunnel junction stack of a magnetic memory cell is disposed within a dielectric layer which serves as a via level of an interlevel dielectric layer with a metal level above the via level. An integration scheme for forming dual damascene structures for interconnects can be formed to logic and memory cells easily.
    Type: Grant
    Filed: September 23, 2015
    Date of Patent: November 6, 2018
    Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.
    Inventors: Juan Boon Tan, Yi Jiang, Daxiang Wang, Fan Zhang, Francis Poh, Danny Pak-Chum Shum
  • Publication number: 20180094196
    Abstract: A method for Fischer-Tropsch synthesis, the method including: 1) gasifying a raw material to obtain a crude syngas including H2, CO and CO2; 2) electrolyzing a saturated NaCl solution using a chloralkali process to obtain a NaOH solution, H2 and H2; 3) removing the CO2 in the crude syngas using the NaOH solution obtained in 2) to obtain a pure syngas; and 4) insufflating the H2 obtained in 2) to the pure syngas to adjust a mole ratio of CO/H2 in the pure syngas, and then introducing the pure syngas for Fischer-Tropsch synthesis reaction. A device for Fischer-Tropsch synthesis includes a gasification device, an electrolyzer, a first gas washing device, and a Fischer-Tropsch synthesis reactor.
    Type: Application
    Filed: December 4, 2017
    Publication date: April 5, 2018
    Inventors: Daxiang WANG, Pingyu Kuai, Meng Li, Yanfeng Zhang
  • Publication number: 20180090505
    Abstract: Methods of producing integrated circuits are provided. An exemplary method includes patterning a source line photoresist mask to overlie a source line area of a substrate while exposing a drain line area. The source line area is between a first and second memory cell and the drain line area is between the second and a third memory cell. A source line is formed in the source line area. A source line dielectric is concurrently formed overlying the source line while a drain line dielectric is formed overlying a drain line area. A drain line photoresist mask is patterned to overlie the source line in an active section while exposing the source line in a strap section, and while exposing the drain line area. The drain line dielectric is removed from over the drain line area while a thickness of the source line dielectric in the strap section is reduced.
    Type: Application
    Filed: September 28, 2016
    Publication date: March 29, 2018
    Inventors: Laiqiang Luo, Yu Jin Eugene Kong, Daxiang Wang, Fan Zhang, Danny Pak-Chum Shum, Pinghui Li, Zhiqiang Teo, Juan Boon Tan, Soh Yun Siah, Pey Kin Leong
  • Patent number: 9929165
    Abstract: Methods of producing integrated circuits are provided. An exemplary method includes patterning a source line photoresist mask to overlie a source line area of a substrate while exposing a drain line area. The source line area is between a first and second memory cell and the drain line area is between the second and a third memory cell. A source line is formed in the source line area. A source line dielectric is concurrently formed overlying the source line while a drain line dielectric is formed overlying a drain line area. A drain line photoresist mask is patterned to overlie the source line in an active section while exposing the source line in a strap section, and while exposing the drain line area. The drain line dielectric is removed from over the drain line area while a thickness of the source line dielectric in the strap section is reduced.
    Type: Grant
    Filed: September 28, 2016
    Date of Patent: March 27, 2018
    Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.
    Inventors: Laiqiang Luo, Yu Jin Eugene Kong, Daxiang Wang, Fan Zhang, Danny Pak-Chum Shum, Pinghui Li, Zhiqiang Teo, Juan Boon Tan, Soh Yun Siah, Pey Kin Leong
  • Publication number: 20180012800
    Abstract: Devices and methods for forming a device are disclosed. The method includes providing a substrate having first and second surfaces. At least one through silicon via (TSV) opening is formed in the substrate. The TSV opening extends through the first and second surfaces of the substrate. An alignment trench corresponding to an alignment mark is formed in the substrate. The alignment trench extends from the first surface of the substrate to a depth shallower than a depth of the TSV opening. A dielectric liner layer is provided over the substrate. The dielectric liner layer at least lines sidewalls of the TSV opening. A conductive layer is provided over the substrate. The conductive layer fills at least the TSV opening to form TSV contact. A redistribution layer (RDL) is formed over the substrate. The RDL layer is patterned using a reticle to form at least one opening which corresponds to a TSV contact pad. The reticle is aligned using the alignment mark in the substrate.
    Type: Application
    Filed: September 21, 2017
    Publication date: January 11, 2018
    Inventors: Shunqiang GONG, Juan Boon TAN, Shijie WANG, Mahesh BHATKAR, Daxiang WANG
  • Publication number: 20180009663
    Abstract: A method for drying a catalytic oxidation furnace, the method including: 1) charging a feed gas including oxygen and natural gas, and a temperature control gas to a catalytic oxidation furnace loaded with a catalyst; 2) preheating a mixed gas including the feed gas and the temperature control gas to increase the temperature of the mixed gas, and stopping the preheating when the temperature of the mixed gas achieves a temperature adapted to trigger the oxidation reaction of the mixed gas; and 3) within the molar ratio of the temperature control gas to the feed gas being 0.1-7:1.3-1.6, reducing the molar ratio of the temperature control gas to the feed gas such that the rise of the temperature of the mixed gas conforms to the temperature rising rate of the drying-out curve of a heat insulation refractory material of the catalytic oxidation furnace.
    Type: Application
    Filed: September 24, 2017
    Publication date: January 11, 2018
    Inventors: Yilong CHEN, Yanfeng ZHANG, Pingyu KUAI, Wentang TIAN, Daxiang WANG
  • Patent number: 9793208
    Abstract: A semiconductor device with a temporary discharge path. During back-end-of-line (BEOL), the temporary discharge path discharges a plasma charge collected in a device well, such as a floating p-type well. After processing, the temporary discharge path is rendered non-function, enabling the device to function properly.
    Type: Grant
    Filed: September 29, 2015
    Date of Patent: October 17, 2017
    Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.
    Inventors: Haifeng Sheng, Juan Boon Tan, Wanbing Yi, Daxiang Wang, Soh Yun Siah
  • Patent number: 9793185
    Abstract: Embodiments of a method for forming a device using test structures are presented. The method includes providing a wafer with a device layer. The device layer includes a main device region and a perimeter region. The device layer is patterned with active and test patterns. Test patterns include dummy patterns disposed in a test device area. The wafer is processed to form at least one test device disposed in the perimeter region and one or more active devices disposed in the main device region. The test device determines a design window of the one or more active devices. Additional processing is performed to complete forming the device.
    Type: Grant
    Filed: November 12, 2014
    Date of Patent: October 17, 2017
    Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.
    Inventors: Wanbing Yi, Daxiang Wang, Juan Boon Tan, Kemao Lin, Shaoqiang Zhang
  • Patent number: 9773702
    Abstract: Devices and methods for forming a device are disclosed. The method includes providing a substrate having first and second surfaces. At least one through silicon via (TSV) opening is formed in the substrate. The TSV opening extends through the first and second surfaces of the substrate. An alignment trench corresponding to an alignment mark is formed in the substrate. The alignment trench extends from the first surface of the substrate to a depth shallower than a depth of the TSV opening. A dielectric liner layer is provided over the substrate. The dielectric liner layer at least lines sidewalls of the TSV opening. A conductive layer is provided over the substrate. The conductive layer fills at least the TSV opening to form TSV contact. A redistribution layer (RDL) is formed over the substrate. The RDL layer is patterned using a reticle to form at least one opening which corresponds to a TSV contact pad. The reticle is aligned using the alignment mark in the substrate.
    Type: Grant
    Filed: December 28, 2015
    Date of Patent: September 26, 2017
    Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.
    Inventors: Shunqiang Gong, Juan Boon Tan, Shijie Wang, Mahesh Bhatkar, Daxiang Wang
  • Publication number: 20170092584
    Abstract: A semiconductor device with a temporary discharge path. During back-end-of-line (BEOL), the temporary discharge path discharges a plasma charge collected in a device well, such as a floating p-type well. After processing, the temporary discharge path is rendered non-function, enabling the device to function properly.
    Type: Application
    Filed: September 29, 2015
    Publication date: March 30, 2017
    Inventors: Haifeng SHENG, Juan Boon TAN, Wanbing YI, Daxiang WANG, Soh Yun SIAH
  • Publication number: 20170084820
    Abstract: Integrating magnetic random access memory with logic is disclosed. The magnetic tunnel junction stack of a magnetic memory cell is disposed within a dielectric layer which serves as a via level of an interlevel dielectric layer with a metal level above the via level. An integration scheme for forming dual damascene structures for interconnects can be formed to logic and memory cells easily.
    Type: Application
    Filed: September 23, 2015
    Publication date: March 23, 2017
    Inventors: Juan Boon TAN, Yi JIANG, Daxiang WANG, Fan ZHANG, Francis POH, Danny Pak-Chum SHUM
  • Publication number: 20160351797
    Abstract: Device and methods of forming a device are disclosed. The method includes providing a substrate defined with at least first and second regions. A first dielectric layer is provided over the first and second regions of the substrate. The first dielectric layer corresponds to pre-metal dielectric (PMD) or CA level which comprises a plurality of contact plugs in the first and second regions. A first interlevel dielectric (ILD) layer is provided over the first dielectric layer. The first ILD layer accommodates a plurality of metal lines in M1 metal level in the first and second regions and via contact in V0 via level in the first region. A magnetic random access memory (MRAM) cell is formed in the second region. The MRAM cell includes a magnetic tunnel junction (MTJ) element sandwiched between the M1 metal level and CA level.
    Type: Application
    Filed: May 26, 2016
    Publication date: December 1, 2016
    Inventors: Wanbing YI, Yi JIANG, Daxiang WANG, Wei SHAO, Juan Boon TAN
  • Publication number: 20160190041
    Abstract: Devices and methods for forming a device are disclosed. The method includes providing a substrate having first and second surfaces. At least one through silicon via (TSV) opening is formed in the substrate. The TSV opening extends through the first and second surfaces of the substrate. An alignment trench corresponding to an alignment mark is formed in the substrate. The alignment trench extends from the first surface of the substrate to a depth shallower than a depth of the TSV opening. A dielectric liner layer is provided over the substrate. The dielectric liner layer at least lines sidewalls of the TSV opening. A conductive layer is provided over the substrate. The conductive layer fills at least the TSV opening to form TSV contact. A redistribution layer (RDL) is formed over the substrate. The RDL layer is patterned using a reticle to form at least one opening which corresponds to a TSV contact pad. The reticle is aligned using the alignment mark in the substrate.
    Type: Application
    Filed: December 28, 2015
    Publication date: June 30, 2016
    Inventors: Shunqiang Gong, Juan Boon Tan, Shijie Wang, Mahesh Bhatkar, Daxiang Wang
  • Publication number: 20160133531
    Abstract: Embodiments of a method for forming a device using test structures are presented. The method includes providing a wafer with a device layer. The device layer includes a main device region and a perimeter region. The device layer is patterned with active and test patterns. Test patterns include dummy patterns disposed in a test device area. The wafer is processed to form at least one test device disposed in the perimeter region and one or more active devices disposed in the main device region. The test device determines a design window of the one or more active devices. Additional processing is performed to complete forming the device.
    Type: Application
    Filed: November 12, 2014
    Publication date: May 12, 2016
    Inventors: Wanbing YI, Daxiang WANG, Juan Boon TAN, Kemao LIN, Shaoqiang ZHANG
  • Patent number: 9192891
    Abstract: Methods for control of NOx emission in the incineration of tail gas are provided wherein tail gas that comprises NOx, NOx precursors, or both is introduced into a combustor and diluent is introduced into the combustor for controlling the combustor temperature to a temperature of from about 950° C. to about 1100° C. Methods also are provided for reducing NOx emissions by controlling air-to-fuel ratio in a tail gas combustor while controlling the combustor flame temperature through diluent injections. A boiler unit for carrying out these methods also is provided. A system for carbon black production using the boiler unit also is provided.
    Type: Grant
    Filed: November 8, 2011
    Date of Patent: November 24, 2015
    Assignee: CABOT CORPORATION
    Inventors: William R. Williams, Daxiang Wang, Theis F. Clarke
  • Publication number: 20130230432
    Abstract: Methods for control of NOx emission in the incineration of tail gas are provided wherein tail gas that comprises NOx, NOx precursors, or both is introduced into a combustor and diluent is introduced into the combustor for controlling the combustor temperature to a temperature of from about 950° C. to about 1100° C. Methods also are provided for reducing NOx emissions by controlling air-to-fuel ratio in a tail gas combustor while controlling the combustor flame temperature through diluent injections. A boiler unit for carrying out these methods also is provided. A system for carbon black production using the boiler unit also is provided.
    Type: Application
    Filed: November 8, 2011
    Publication date: September 5, 2013
    Applicant: CABOT CORPORATION
    Inventors: William R. Williams, Daxiang Wang, Theis F. Clarke
  • Patent number: 7524786
    Abstract: The present invention relates to a process for the preparation of synthesis gas (i.e., a mixture of carbon monoxide and hydrogen), typically labeled syngas. More particularly, the present invention relates to a regeneration method for a syngas catalyst. Still more particularly, the present invention relates to the regeneration of syngas catalysts using a re-dispersion technique. One embodiment of the re-dispersion technique involves the treatment of a deactivated syngas catalyst with a re-dispersing gas, preferably a carbon monoxide-containing gas such as syngas. If necessary, the catalyst is then exposed to hydrogen for reduction and further re-dispersion.
    Type: Grant
    Filed: April 25, 2005
    Date of Patent: April 28, 2009
    Assignee: ConocoPhillips Company
    Inventors: Daxiang Wang, Baili Hu, Yaming Jin, Harold A. Wright