Abstract: Integrating magnetic random access memory with logic is disclosed. The magnetic tunnel junction stack of a magnetic memory cell is disposed within a dielectric layer which serves as a via level of an interlevel dielectric layer with a metal level above the via level. An integration scheme for forming dual damascene structures for interconnects can be formed to logic and memory cells easily.

Abstract: A method for Fischer-Tropsch synthesis, the method including: 1) gasifying a raw material to obtain a crude syngas including H2, CO and CO2; 2) electrolyzing a saturated NaCl solution using a chloralkali process to obtain a NaOH solution, H2 and H2; 3) removing the CO2 in the crude syngas using the NaOH solution obtained in 2) to obtain a pure syngas; and 4) insufflating the H2 obtained in 2) to the pure syngas to adjust a mole ratio of CO/H2 in the pure syngas, and then introducing the pure syngas for Fischer-Tropsch synthesis reaction. A device for Fischer-Tropsch synthesis includes a gasification device, an electrolyzer, a first gas washing device, and a Fischer-Tropsch synthesis reactor.

Abstract: Methods of producing integrated circuits are provided. An exemplary method includes patterning a source line photoresist mask to overlie a source line area of a substrate while exposing a drain line area. The source line area is between a first and second memory cell and the drain line area is between the second and a third memory cell. A source line is formed in the source line area. A source line dielectric is concurrently formed overlying the source line while a drain line dielectric is formed overlying a drain line area. A drain line photoresist mask is patterned to overlie the source line in an active section while exposing the source line in a strap section, and while exposing the drain line area. The drain line dielectric is removed from over the drain line area while a thickness of the source line dielectric in the strap section is reduced.

Abstract: Methods of producing integrated circuits are provided. An exemplary method includes patterning a source line photoresist mask to overlie a source line area of a substrate while exposing a drain line area. The source line area is between a first and second memory cell and the drain line area is between the second and a third memory cell. A source line is formed in the source line area. A source line dielectric is concurrently formed overlying the source line while a drain line dielectric is formed overlying a drain line area. A drain line photoresist mask is patterned to overlie the source line in an active section while exposing the source line in a strap section, and while exposing the drain line area. The drain line dielectric is removed from over the drain line area while a thickness of the source line dielectric in the strap section is reduced.

Abstract: Devices and methods for forming a device are disclosed. The method includes providing a substrate having first and second surfaces. At least one through silicon via (TSV) opening is formed in the substrate. The TSV opening extends through the first and second surfaces of the substrate. An alignment trench corresponding to an alignment mark is formed in the substrate. The alignment trench extends from the first surface of the substrate to a depth shallower than a depth of the TSV opening. A dielectric liner layer is provided over the substrate. The dielectric liner layer at least lines sidewalls of the TSV opening. A conductive layer is provided over the substrate. The conductive layer fills at least the TSV opening to form TSV contact. A redistribution layer (RDL) is formed over the substrate. The RDL layer is patterned using a reticle to form at least one opening which corresponds to a TSV contact pad. The reticle is aligned using the alignment mark in the substrate.

Abstract: A method for drying a catalytic oxidation furnace, the method including: 1) charging a feed gas including oxygen and natural gas, and a temperature control gas to a catalytic oxidation furnace loaded with a catalyst; 2) preheating a mixed gas including the feed gas and the temperature control gas to increase the temperature of the mixed gas, and stopping the preheating when the temperature of the mixed gas achieves a temperature adapted to trigger the oxidation reaction of the mixed gas; and 3) within the molar ratio of the temperature control gas to the feed gas being 0.1-7:1.3-1.6, reducing the molar ratio of the temperature control gas to the feed gas such that the rise of the temperature of the mixed gas conforms to the temperature rising rate of the drying-out curve of a heat insulation refractory material of the catalytic oxidation furnace.

Abstract: Embodiments of a method for forming a device using test structures are presented. The method includes providing a wafer with a device layer. The device layer includes a main device region and a perimeter region. The device layer is patterned with active and test patterns. Test patterns include dummy patterns disposed in a test device area. The wafer is processed to form at least one test device disposed in the perimeter region and one or more active devices disposed in the main device region. The test device determines a design window of the one or more active devices. Additional processing is performed to complete forming the device.

Abstract: A semiconductor device with a temporary discharge path. During back-end-of-line (BEOL), the temporary discharge path discharges a plasma charge collected in a device well, such as a floating p-type well. After processing, the temporary discharge path is rendered non-function, enabling the device to function properly.

Abstract: Devices and methods for forming a device are disclosed. The method includes providing a substrate having first and second surfaces. At least one through silicon via (TSV) opening is formed in the substrate. The TSV opening extends through the first and second surfaces of the substrate. An alignment trench corresponding to an alignment mark is formed in the substrate. The alignment trench extends from the first surface of the substrate to a depth shallower than a depth of the TSV opening. A dielectric liner layer is provided over the substrate. The dielectric liner layer at least lines sidewalls of the TSV opening. A conductive layer is provided over the substrate. The conductive layer fills at least the TSV opening to form TSV contact. A redistribution layer (RDL) is formed over the substrate. The RDL layer is patterned using a reticle to form at least one opening which corresponds to a TSV contact pad. The reticle is aligned using the alignment mark in the substrate.

Abstract: A semiconductor device with a temporary discharge path. During back-end-of-line (BEOL), the temporary discharge path discharges a plasma charge collected in a device well, such as a floating p-type well. After processing, the temporary discharge path is rendered non-function, enabling the device to function properly.

Abstract: Integrating magnetic random access memory with logic is disclosed. The magnetic tunnel junction stack of a magnetic memory cell is disposed within a dielectric layer which serves as a via level of an interlevel dielectric layer with a metal level above the via level. An integration scheme for forming dual damascene structures for interconnects can be formed to logic and memory cells easily.

Abstract: Device and methods of forming a device are disclosed. The method includes providing a substrate defined with at least first and second regions. A first dielectric layer is provided over the first and second regions of the substrate. The first dielectric layer corresponds to pre-metal dielectric (PMD) or CA level which comprises a plurality of contact plugs in the first and second regions. A first interlevel dielectric (ILD) layer is provided over the first dielectric layer. The first ILD layer accommodates a plurality of metal lines in M1 metal level in the first and second regions and via contact in V0 via level in the first region. A magnetic random access memory (MRAM) cell is formed in the second region. The MRAM cell includes a magnetic tunnel junction (MTJ) element sandwiched between the M1 metal level and CA level.

Abstract: Devices and methods for forming a device are disclosed. The method includes providing a substrate having first and second surfaces. At least one through silicon via (TSV) opening is formed in the substrate. The TSV opening extends through the first and second surfaces of the substrate. An alignment trench corresponding to an alignment mark is formed in the substrate. The alignment trench extends from the first surface of the substrate to a depth shallower than a depth of the TSV opening. A dielectric liner layer is provided over the substrate. The dielectric liner layer at least lines sidewalls of the TSV opening. A conductive layer is provided over the substrate. The conductive layer fills at least the TSV opening to form TSV contact. A redistribution layer (RDL) is formed over the substrate. The RDL layer is patterned using a reticle to form at least one opening which corresponds to a TSV contact pad. The reticle is aligned using the alignment mark in the substrate.

Abstract: Embodiments of a method for forming a device using test structures are presented. The method includes providing a wafer with a device layer. The device layer includes a main device region and a perimeter region. The device layer is patterned with active and test patterns. Test patterns include dummy patterns disposed in a test device area. The wafer is processed to form at least one test device disposed in the perimeter region and one or more active devices disposed in the main device region. The test device determines a design window of the one or more active devices. Additional processing is performed to complete forming the device.

Abstract: Methods for control of NOx emission in the incineration of tail gas are provided wherein tail gas that comprises NOx, NOx precursors, or both is introduced into a combustor and diluent is introduced into the combustor for controlling the combustor temperature to a temperature of from about 950° C. to about 1100° C. Methods also are provided for reducing NOx emissions by controlling air-to-fuel ratio in a tail gas combustor while controlling the combustor flame temperature through diluent injections. A boiler unit for carrying out these methods also is provided. A system for carbon black production using the boiler unit also is provided.

Abstract: Methods for control of NOx emission in the incineration of tail gas are provided wherein tail gas that comprises NOx, NOx precursors, or both is introduced into a combustor and diluent is introduced into the combustor for controlling the combustor temperature to a temperature of from about 950° C. to about 1100° C. Methods also are provided for reducing NOx emissions by controlling air-to-fuel ratio in a tail gas combustor while controlling the combustor flame temperature through diluent injections. A boiler unit for carrying out these methods also is provided. A system for carbon black production using the boiler unit also is provided.

Abstract: The present invention relates to a process for the preparation of synthesis gas (i.e., a mixture of carbon monoxide and hydrogen), typically labeled syngas. More particularly, the present invention relates to a regeneration method for a syngas catalyst. Still more particularly, the present invention relates to the regeneration of syngas catalysts using a re-dispersion technique. One embodiment of the re-dispersion technique involves the treatment of a deactivated syngas catalyst with a re-dispersing gas, preferably a carbon monoxide-containing gas such as syngas. If necessary, the catalyst is then exposed to hydrogen for reduction and further re-dispersion.

Abstract: Controlled pore structure catalysts are disclosed that are active for catalyzing the partial oxidation of methane to CO and H2 and, advantageously, are capable of initiating the reaction without the need for an additional ignition source. A preferred catalyst comprises rhodium and samarium supported on an alumina or modified alumina support having certain surface area, pore volume, pore size and metal dispersion characteristics that permit light-off of the reaction at temperatures below 500° C. and with little or no use of an ignition agent. A method of partially oxidizing a light hydrocarbon to form synthesis gas, and a method of enhancing low-temperature light-off of the process are also described.

Abstract: A porous catalyst support having an increased average pore size is produced from a mixed metal oxide material. In accordance with one embodiment, a method for preparing a mixed metal oxide material includes providing a mixed metal oxide precursor containing at least two metals, calcining the mixed metal oxide precursor at a temperature sufficient to form a thermally and mechanically stable mixed metal oxide material, and leaching the mixed metal oxide material in a leach solution with a constituent that dissolves one metal oxide. Preferably, the calcination temperature is approximately between 300° C. and 1300° C. The leaching constituent may be chosen from the group including acidic solutions of HCl, HNO3, H2SO4, H3PO3, and their combinations, or basic solutions of NH3, NaOH, KOH, and their combinations.

Abstract: The present invention is an improvement in the preparation of liquid hydrocarbons from natural gas/methane, oxygen and/or steam. In particular, the present invention relates to processes for the production of synthesis gas, reducing the oxygen concentration from the synthesis gas, and the production of liquid hydrocarbons using the oxygen reduced synthesis gas as a feedstock. More particularly, the present invention described herein identifies catalyst compositions, apparatus and methods of using such catalysts and apparatus for preparing liquid hydrocarbons via oxygen reduced synthesis gas all in accordance with the present invention.