Patents by Inventor De-Fang Chen
De-Fang Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20180240882Abstract: According to an exemplary embodiment, a method of forming a vertical structure with at least two barrier layers is provided. The method includes the following operations: providing a substrate; providing a vertical structure over the substrate; providing a first barrier layer over a source, a channel, and a drain of the vertical structure; and providing a second barrier layer over a gate and the drain of the vertical structure.Type: ApplicationFiled: April 23, 2018Publication date: August 23, 2018Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chih-Tang PENG, Tai-Chun HUANG, Teng-Chun TSAI, Cheng-Tung LIN, De-Fang CHEN, Li-Ting WANG, Chien-Hsun WANG, Huan-Just LIN, Yung-Cheng LU, Tze-Liang LEE
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Publication number: 20180218904Abstract: A method of forming an integrated circuit includes forming a patterned mask layer on a material layer, wherein the patterned mask layer has a plurality of first features, and a first distance between adjacent first features of the plurality of first features. The method further includes patterning the material layer to form the first features in the material layer. The method further includes increasing the first distance between adjacent first features of the plurality of first features to a second distance. The method further includes treating portions of the material layer exposed by the patterned mask layer. The method further includes removing the patterned mask layer; and removing non-treated portions of the material layer.Type: ApplicationFiled: March 29, 2018Publication date: August 2, 2018Inventors: Tzu-Yen Hsieh, Ming-Ching Chang, Chun-Hung Lee, Yih-Ann Lin, De-Fang Chen, Chao-Cheng Chen
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Patent number: 10032639Abstract: Exemplary methods of patterning a device layer are described, including operations of patterning a protector layer and forming a first opening in a first patterning layer to expose a first portion of the protector layer and a first portion of the hard mask layer, which are then are exposed to a first etch to form a first opening in the first portion of the hard mask layer. A second opening is formed in a second patterning layer to expose a second portion of the protector layer and a second portion of the hard mask layer. The second portion of the protector layer and the second portion of the hard mask layer are exposed to an etch to form a second opening in the second portion of the hard mask layer. Exposed portions of the device layer are then etched through the first opening and the second opening.Type: GrantFiled: May 31, 2016Date of Patent: July 24, 2018Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chi-Cheng Hung, Chun-Kuang Chen, De-Fang Chen, Wei-Liang Lin, Yu-Tien Shen
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Patent number: 10026658Abstract: Systems and methods are provided for fabricating nanowire devices on a substrate. A first nanowire and a second nanowire are formed on a substrate, the first nanowire and the second nanowire extending substantially vertically relative to the substrate. A first source region and a first drain region are formed with n-type dopants, the first nanowire being disposed between the first source region and the first drain region. A second source region and a second drain region are formed with p-type dopants, the second nanowire being disposed between the second source region and the second drain region.Type: GrantFiled: April 14, 2014Date of Patent: July 17, 2018Assignee: Taiwan Semiconductor Manufacturing Company LimitedInventors: Teng-Chun Tsai, Cheng-Tung Lin, Li-Ting Wang, De-Fang Chen, Huan-Just Lin
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Patent number: 9991132Abstract: A technique for patterning a workpiece such as an integrated circuit workpiece is provided. In an exemplary embodiment, the method includes receiving a workpiece having a material layer disposed on a substrate. A first set of fins is formed on the material layer, and a second set of fins is formed on the material layer interspersed between the first set of fins. The second set of fins have a different etchant sensitivity from the first set of fins. A first etching process is performed on the first set of fins and configured to avoid substantial etching of the second set of fins. A second etching process is performed on the second set of fins and configured to avoid substantial etching of the first set of fins. The material layer is etched to transfer a pattern defined by the first etching process and the second etching process.Type: GrantFiled: April 17, 2015Date of Patent: June 5, 2018Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chin-Yuan Tseng, Chi-Cheng Hung, Chun-Kuang Chen, De-Fang Chen, Ru-Gun Liu, Tsai-Sheng Gau, Wei-Liang Lin
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Patent number: 9966448Abstract: According to an exemplary embodiment, a method of forming a vertical structure is provided. The method includes the following operations: providing a substrate; providing the vertical structure with a source and a channel over the substrate; forming a spacer over the vertical structure; etching a portion of the spacer to expose the source; forming a first metal layer over the vertical structure; and thermal annealing the first metal layer to form a bottom silicide penetrating the source; and substantially removing the spacer.Type: GrantFiled: May 16, 2014Date of Patent: May 8, 2018Assignee: Taiwan Semiconductor Manufacturing Company LimitedInventors: Cheng-Tung Lin, Teng-Chun Tsai, Li-Ting Wang, De-Fang Chen, Huang-Yi Huang, Hui-Cheng Chang, Huan-Just Lin, Ming-Hsing Tsai
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Patent number: 9954069Abstract: A semiconductor device includes a source/drain region, a barrier layer, and an interlayer dielectric. The barrier layer surrounds the source/drain region. The interlayer dielectric surrounds the barrier layer. As such, the source/drain region can be protected by the barrier layer from oxidation during manufacturing of the semiconductor device, e.g., the formation of the interlayer dielectric.Type: GrantFiled: March 30, 2016Date of Patent: April 24, 2018Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chih-Tang Peng, Tai-Chun Huang, Teng-Chun Tsai, Cheng-Tung Lin, De-Fang Chen, Li-Ting Wang, Chien-Hsun Wang, Huan-Just Lin, Yung-Cheng Lu, Tze-Liang Lee
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Patent number: 9941394Abstract: The tunnel field-effect transistor includes a drain layer, a source layer, a channel layer, a metal gate layer, and a high-k dielectric layer. The drain and source layers are of opposite conductive types. The channel layer is disposed between the drain layer and the source layer. At least one of the drain layer, the channel layer, and the source layer has a substantially constant doping concentration. The metal gate layer is disposed around the channel layer. The high-k dielectric layer is disposed between the metal gate layer and the channel layer.Type: GrantFiled: August 14, 2014Date of Patent: April 10, 2018Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Teng-Chun Tsai, Cheng-Tung Lin, Li-Ting Wang, Chih-Tang Peng, De-Fang Chen, Hung-Ta Lin, Chien-Hsun Wang
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Patent number: 9934971Abstract: A method of forming an integrated circuit includes forming a patterned mask layer on a material layer, wherein the patterned mask layer has a plurality of first features, and a first distance between adjacent first features of the plurality of first features. The method further includes patterning the material layer to form the first features in the material layer. The method further includes increasing the first distance between adjacent first features of the plurality of first features to a second distance. The method further includes treating portions of the material layer exposed by the patterned mask layer. The method further includes removing the patterned mask layer; and removing non-treated portions of the material layer.Type: GrantFiled: May 1, 2017Date of Patent: April 3, 2018Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Tzu-Yen Hsieh, Ming-Ching Chang, Chun-Hung Lee, Yih-Ann Lin, De-Fang Chen, Chao-Cheng Chen
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Patent number: 9911661Abstract: A method includes depositing a sacrificial layer on a first dielectric layer over a substrate; applying a first patterning process, a second patterning process, a third patterning process to the sacrificial layer to form a first group of openings, a second group of openings and a third group of openings, respectively, in the sacrificial layer, wherein three first openings from three different patterning processes form a first side, a second side and a first angle between the first side and the second side, and three second openings from the three different patterning processes form a third side, a fourth side and a second angle between the third side and the fourth side, wherein the first angle is approximately equal to the second angle and forming nanowires based on the first group of openings, the second group of openings and the third group of openings.Type: GrantFiled: August 18, 2017Date of Patent: March 6, 2018Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Ching-Feng Fu, De-Fang Chen, Yu-Chan Yen, Chia-Ying Lee, Chun-Hung Lee, Huan-Just Lin
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Patent number: 9853102Abstract: A tunnel field-effect transistor and method fabricating the same are provided. The tunnel field-effect transistor includes a drain region, a source region with opposite conductive type to the drain region, a channel region disposed between the drain region and the source region, a metal gate layer disposed around the channel region, and a high-k dielectric layer disposed between the metal gate layer and the channel region.Type: GrantFiled: August 8, 2014Date of Patent: December 26, 2017Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Teng-Chun Tsai, Li-Ting Wang, Cheng-Tung Lin, De-Fang Chen, Chih-Tang Peng, Chien-Hsun Wang, Hung-Ta Lin
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Publication number: 20170365524Abstract: A method includes depositing a sacrificial layer on a first dielectric layer over a substrate; applying a first patterning process, a second patterning process, a third patterning process to the sacrificial layer to form a first group of openings, a second group of openings and a third group of openings, respectively, in the sacrificial layer, wherein three first openings from three different patterning processes form a first side, a second side and a first angle between the first side and the second side, and three second openings from the three different patterning processes form a third side, a fourth side and a second angle between the third side and the fourth side, wherein the first angle is approximately equal to the second angle and forming nanowires based on the first group of openings, the second group of openings and the third group of openings.Type: ApplicationFiled: August 18, 2017Publication date: December 21, 2017Inventors: Ching-Feng Fu, De-Fang Chen, Yu-Chan Yen, Chia-Ying Lee, Chun-Hung Lee, Huan-Just Lin
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Publication number: 20170345670Abstract: Exemplary methods of patterning a device layer are described, including operations of patterning a protector layer and forming a first opening in a first patterning layer to expose a first portion of the protector layer and a first portion of the hard mask layer, which are then are exposed to a first etch to form a first opening in the first portion of the hard mask layer. A second opening is formed in a second patterning layer to expose a second portion of the protector layer and a second portion of the hard mask layer. The second portion of the protector layer and the second portion of the hard mask layer are exposed to an etch to form a second opening in the second portion of the hard mask layer. Exposed portions of the device layer are then etched through the first opening and the second opening.Type: ApplicationFiled: May 31, 2016Publication date: November 30, 2017Inventors: Chi-Cheng Hung, Chun-Kuang Chen, De-Fang Chen, Wei-Liang Lin, Yu-Tien Shen
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Patent number: 9805968Abstract: According to an exemplary embodiment, a method of forming a semiconductor device is provided. The method includes: providing a vertical structure over a substrate; forming an etch stop layer over the vertical structure; forming an oxide layer over the etch stop layer; performing chemical mechanical polishing on the oxide layer and stopping on the etch stop layer; etching back the oxide layer and the etch stop layer to expose a sidewall of the vertical structure and to form an isolation layer; oxidizing the sidewall of the vertical structure and doping oxygen into the isolation layer by using a cluster oxygen doping treatment.Type: GrantFiled: February 13, 2017Date of Patent: October 31, 2017Assignee: Taiwan Semiconductor Manufacturing Company LimitedInventors: Cheng-Tung Lin, Teng-Chun Tsai, Li-Ting Wang, De-Fang Chen, Bing-Hung Chen, Huang-Yi Huang, Hui-Cheng Chang, Huan-Just Lin, Ming-Hsing Tsai
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Patent number: 9741621Abstract: A method comprises depositing a sacrificial layer on a first dielectric layer over a substrate, applying a first patterning process, a second patterning process, a third patterning process and a fourth patterning process to the sacrificial layer to form a first group of openings, a second group of openings, a third group of openings and a fourth group of openings, respectively, in the sacrificial layer, wherein openings from different patterning processes are arranged in an alternating manner and four openings of the opening from the different patterning processes form a diamond shape and forming nanowires based on the first group of openings, the second group of openings, the third group of openings and the fourth group of openings.Type: GrantFiled: February 10, 2017Date of Patent: August 22, 2017Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Ching-Feng Fu, De-Fang Chen, Yu-Chan Yen, Chia-Ying Lee, Chun-Hung Lee, Huan-Just Lin
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Publication number: 20170236712Abstract: A method of forming an integrated circuit includes forming a patterned mask layer on a material layer, wherein the patterned mask layer has a plurality of first features, and a first distance between adjacent first features of the plurality of first features. The method further includes patterning the material layer to form the first features in the material layer. The method further includes increasing the first distance between adjacent first features of the plurality of first features to a second distance. The method further includes treating portions of the material layer exposed by the patterned mask layer. The method further includes removing the patterned mask layer; and removing non-treated portions of the material layer.Type: ApplicationFiled: May 1, 2017Publication date: August 17, 2017Inventors: Tzu-Yen Hsieh, Ming-Ching Chang, Chun-Hung Lee, Yih-Ann Lin, De-Fang Chen, Chao-Cheng Chen
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Patent number: 9733570Abstract: Systems and methods are provided for forming features through photolithography. A polymer layer is formed over a substrate. The polymer layer is patterned to form a first feature and a second feature, the first feature and the second feature being separated at a first distance. A rinse material is applied to the polymer layer including the first feature and the second feature. The rinse material is removed from the polymer layer including the first feature and the second feature to cause the first feature and the second feature to come into contact with each other. A third feature is formed based on the first feature and the second feature being in contact with each other.Type: GrantFiled: October 15, 2015Date of Patent: August 15, 2017Assignee: Taiwan Semiconductor Manufacturing Company LimitedInventors: Chun-Liang Tai, Bi-Ming Yen, Chun-Hung Lee, De-Fang Chen
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Publication number: 20170229349Abstract: A method includes forming a pattern-reservation layer over a semiconductor substrate. The semiconductor substrate has a major surface. A first self-aligned multi-patterning process is performed to pattern a pattern-reservation layer. The remaining portions of the pattern-reservation layer include pattern-reservation strips extending in a first direction that is parallel to the major surface of the semiconductor substrate. A second self-aligned multi-patterning process is performed to pattern the pattern-reservation layer in a second direction parallel to the major surface of the semiconductor substrate. The remaining portions of the pattern-reservation layer include patterned features. The patterned features are used as an etching mask to form semiconductor nanowires by etching the semiconductor substrate.Type: ApplicationFiled: April 24, 2017Publication date: August 10, 2017Inventors: Ching-Feng Fu, De-Fang Chen, Yu-Chan Yen, Chia-Ying Lee, Chun-Hung Lee, Huan-Just Lin
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Publication number: 20170200804Abstract: According to an exemplary embodiment, a method of forming a vertical device is provided. The method includes: providing a protrusion over a substrate; forming an etch stop layer over the protrusion; laterally etching a sidewall of the etch stop layer; forming an insulating layer over the etch stop layer; forming a film layer over the insulating layer and the etch stop layer; performing chemical mechanical polishing on the film layer and exposing the etch stop layer; etching a portion of the etch stop layer to expose a top surface of the protrusion; forming an oxide layer over the protrusion and the film layer; and performing chemical mechanical polishing on the oxide layer and exposing the film layer.Type: ApplicationFiled: March 29, 2017Publication date: July 13, 2017Inventors: DE-FANG CHEN, TENG-CHUN TSAI, CHENG-TUNG LIN, LI-TING WANG, CHUN-HUNG LEE, MING-CHING CHANG, HUAN-JUST LIN
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Patent number: 9685332Abstract: A method for self-aligned patterning includes providing a substrate, forming a patterned mandrel layer that includes a plurality of mandrel features, the patterned mandrel layer being formed on the substrate, depositing a first spacer layer over the mandrel layer, the first spacer layer comprising a first type of material, anisotropically etching the first spacer layer to leave a first set of spacers on sidewalls of the mandrel features, removing the mandrel layer, depositing a second spacer layer over remaining portions of the first set of spacers, and anisotropically etching the second spacer layer to form a second set of spacers on sidewalls of the first set of spacers.Type: GrantFiled: October 17, 2014Date of Patent: June 20, 2017Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: De-Fang Chen, Huan-Just Lin, Chun-Hung Lee, Chao-Cheng Chen