Abstract: A method of forming a channel of a gate structure is provided. A first epitaxial channel layer is formed within a first trench of the gate structure. A dry etching process is performed on the first epitaxial channel layer to form a second trench. A second epitaxial channel layer is formed within the second trench.

Abstract: A method comprises depositing a sacrificial layer on a first dielectric layer over a substrate, applying a first patterning process, a second patterning process, a third patterning process and a fourth patterning process to the sacrificial layer to form a first group of openings, a second group of openings, a third group of openings and a fourth group of openings, respectively, in the sacrificial layer, wherein openings from different patterning processes are arranged in an alternating manner and four openings of the opening from the different patterning processes form a diamond shape and forming nanowires based on the first group of openings, the second group of openings, the third group of openings and the fourth group of openings.

Abstract: According to an exemplary embodiment, a method of forming a semiconductor device is provided. The method includes: providing a vertical structure over a substrate; forming an etch stop layer over the vertical structure; forming an oxide layer over the etch stop layer; performing chemical mechanical polishing on the oxide layer and stopping on the etch stop layer; etching back the oxide layer and the etch stop layer to expose a sidewall of the vertical structure and to form an isolation layer; oxidizing the sidewall of the vertical structure and doping oxygen into the isolation layer by using a cluster oxygen doping treatment.

Abstract: A method of forming an integrated circuit includes forming a patterned mask layer on a material layer, wherein the patterned mask layer has a plurality of first features, and a first distance between adjacent first features of the plurality of first features. The method further includes patterning the material layer to form the first features in the material layer. The method further includes increasing the first distance between adjacent first features of the plurality of first features to a second distance. The method further includes treating portions of the material layer exposed by the patterned mask layer. The method further includes removing the patterned mask layer; and removing non-treated portions of the material layer.

Abstract: A method includes forming a pattern-reservation layer over a semiconductor substrate. The semiconductor substrate has a major surface. A first self-aligned multi-patterning process is performed to pattern a pattern-reservation layer. The remaining portions of the pattern-reservation layer include pattern-reservation strips extending in a first direction that is parallel to the major surface of the semiconductor substrate. A second self-aligned multi-patterning process is performed to pattern the pattern-reservation layer in a second direction parallel to the major surface of the semiconductor substrate. The remaining portions of the pattern-reservation layer include patterned features. The patterned features are used as an etching mask to form semiconductor nanowires by etching the semiconductor substrate.

Abstract: According to an exemplary embodiment, a method of forming a vertical device is provided. The method includes: providing a protrusion over a substrate; forming an etch stop layer over the protrusion; laterally etching a sidewall of the etch stop layer; forming an insulating layer over the etch stop layer; forming a film layer over the insulating layer and the etch stop layer; performing chemical mechanical polishing on the film layer and exposing the etch stop layer; etching a portion of the etch stop layer to expose a top surface of the protrusion; forming an oxide layer over the protrusion and the film layer; and performing chemical mechanical polishing on the oxide layer and exposing the film layer.

Abstract: A method of forming a channel of a gate structure is provided. A first epitaxial channel layer is formed within a first trench of the gate structure. A dry etching process is performed on the first epitaxial channel layer to form a second trench. A second epitaxial channel layer is formed within the second trench.

Abstract: According to an exemplary embodiment, a method of forming a semiconductor device is provided. The method includes: providing a vertical structure over a substrate; forming an etch stop layer over the vertical structure; forming an oxide layer over the etch stop layer; performing chemical mechanical polishing on the oxide layer and stopping on the etch stop layer; etching back the oxide layer and the etch stop layer to expose a sidewall of the vertical structure and to form an isolation layer; oxidizing the sidewall of the vertical structure and doping oxygen into the isolation layer by using a cluster oxygen doping treatment.

Abstract: A method comprises applying a first patterning process to a first photoresist layer to form a first opening, a second opening, a third opening and a fourth opening in the sacrificial layer, applying a second patterning process to a second photoresist layer to form a fifth opening, a sixth opening, a seventh opening and an eighth opening in the sacrificial layer, wherein distances between two adjacent openings formed from the first and second patterning processes are substantially equal to each other, applying a third patterning process to a third photoresist layer to form a ninth opening, a tenth opening, an eleventh opening and a twelfth opening in the sacrificial layer, wherein distances between two adjacent openings formed from the second and third patterning processes are substantially equal to each other and forming a plurality of nanowires based on the openings.

Abstract: According to an exemplary embodiment, a method of forming vertical structures is provided. The method includes the following operations: providing a substrate; forming a first oxide layer over the substrate; forming a first dummy layer over the first oxide layer; etching the first oxide layer and the first dummy layer to form a recess; forming a second dummy layer in the recess (and further performing CMP on the second dummy layer and stop on the first dummy layer); removing the first dummy layer; removing the first oxide layer; and etching the substrate to form the vertical structure. According to an exemplary embodiment, a semiconductor device is provided. The semiconductor device includes: a substrate; an STI embedded in the substrate; and a vertical transistor having a source substantially aligned with the STI.

Abstract: A method comprises applying a first patterning process to a first photoresist layer to form a first opening, a second opening, a third opening and a fourth opening in the sacrificial layer, applying a second patterning process to a second photoresist layer to form a fifth opening, a sixth opening, a seventh opening and an eighth opening in the sacrificial layer, wherein distances between two adjacent openings formed from the first and second patterning processes are substantially equal to each other, applying a third patterning process to a third photoresist layer to form a ninth opening, a tenth opening, an eleventh opening and a twelfth opening in the sacrificial layer, wherein distances between two adjacent openings formed from the second and third patterning processes are substantially equal to each other and forming a plurality of nanowires based on the openings.

Abstract: Structures and methods are provided for forming bottom source/drain contact regions for nanowire devices. A nanowire is formed on a substrate. The nanowire extends substantially vertically relative to the substrate and is disposed between a top source/drain region and a bottom source/drain region. A first dielectric material is formed on the bottom source/drain region. A second dielectric material is formed on the first dielectric material. A first etching process is performed to remove part of the first dielectric material and part of the second dielectric material to expose part of the bottom source/drain region. A second etching process is performed to remove part of the first dielectric material under the second dielectric material to further expose the bottom source/drain region. A first metal-containing material is formed on the exposed bottom source/drain region. Annealing is performed to form a bottom contact region.

Abstract: A technique for patterning a workpiece such as an integrated circuit workpiece is provided. In an exemplary embodiment, the method includes receiving a workpiece having a material layer disposed on a substrate. A first set of fins is formed on the material layer, and a second set of fins is formed on the material layer interspersed between the first set of fins. The second set of fins have a different etchant sensitivity from the first set of fins. A first etching process is performed on the first set of fins and configured to avoid substantial etching of the second set of fins. A second etching process is performed on the second set of fins and configured to avoid substantial etching of the first set of fins. The material layer is etched to transfer a pattern defined by the first etching process and the second etching process.

Abstract: Embodiments of the present disclosure are a method of forming a semiconductor device and methods of patterning a semiconductor device. An embodiment is a method of forming a semiconductor device, the method including pattering a mandrel layer disposed over a semiconductor device layer to form a mandrel, forming a first set of spacers on sidewalls of the mandrel using a first material, selectively removing the mandrel disposed between the first set of spacers. The method further includes after removing the mandrel, using the first set of spacers as a first set of mandrels, forming a second set of spacers on sidewalls of the first set of mandrels using a second material, the second material having a different etch selectivity from the etch selectivity of the first material, the second set of spacers have substantially flat top surfaces, and selectively removing the first set of mandrels disposed between the second set of spacers.

Abstract: According to an exemplary embodiment, a semiconductor device is provided. The semiconductor device includes: a substrate; a first vertical structure protruding from the substrate; a second vertical structure protruding from the substrate; an STI between the first vertical structure and the second vertical structure; wherein a first horizontal width between the first vertical structure and the STI is substantially the same as a second horizontal width between the second vertical structure and the STI.

Abstract: Embodiments of the present disclosure are a method of forming a semiconductor device and methods of patterning a semiconductor device. An embodiment is a method of forming a semiconductor device, the method including pattering a mandrel layer disposed over a semiconductor device layer to form a mandrel, forming a first set of spacers on sidewalls of the mandrel using a first material, selectively removing the mandrel disposed between the first set of spacers. The method further includes after removing the mandrel, using the first set of spacers as a first set of mandrels, forming a second set of spacers on sidewalls of the first set of mandrels using a second material, the second material having a different etch selectivity from the etch selectivity of the first material, the second set of spacers have substantially flat top surfaces, and selectively removing the first set of mandrels disposed between the second set of spacers.

Abstract: A device comprises a first group of nanowires having a first pattern, a second group of nanowires having a second pattern, a third group of nanowires having a third pattern and a fourth group of nanowires having a fourth pattern, wherein the first pattern, the second pattern, the third pattern and the fourth pattern form a repeating pattern.

Abstract: A semiconductor device includes a source/drain region, a barrier layer, and an interlayer dielectric. The barrier layer surrounds the source/drain region. The interlayer dielectric surrounds the barrier layer. As such, the source/drain region can be protected by the barrier layer from oxidation during manufacturing of the semiconductor device, e.g., the formation of the interlayer dielectric.

Abstract: A method for self-aligned patterning includes providing a substrate, forming a patterned mandrel layer that includes a plurality of mandrel features, the patterned mandrel layer being formed on the substrate, depositing a first spacer layer over the mandrel layer, the first spacer layer comprising a first type of material, anisotropically etching the first spacer layer to leave a first set of spacers on sidewalls of the mandrel features, removing the mandrel layer, depositing a second spacer layer over remaining portions of the first set of spacers, and anisotropically etching the second spacer layer to form a second set of spacers on sidewalls of the first set of spacers.

Abstract: According to an exemplary embodiment, a method of forming a vertical device is provided. The method includes: providing a protrusion over a substrate; forming an etch stop layer over the protrusion; laterally etching a sidewall of the etch stop layer; forming an insulating layer over the etch stop layer; forming a film layer over the insulating layer and the etch stop layer; performing chemical mechanical polishing on the film layer and exposing the etch stop layer; etching a portion of the etch stop layer to expose a top surface of the protrusion; forming an oxide layer over the protrusion and the film layer; and performing chemical mechanical polishing on the oxide layer and exposing the film layer.