Patents by Inventor De Wang

De Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250151433
    Abstract: A pixel array that includes some pixels with high absorption (HA) structures and other pixels without HA structures exhibits increased dynamic range for near infrared (NIR) light. Additionally, the pixel array is a uniform array of photodiodes and thus does not exhibit current leakage that would have been caused by irregular isolation structures. Additionally, the pixel array may further a lateral overflow integration capacitor to further increase the dynamic range for NIR light.
    Type: Application
    Filed: November 3, 2023
    Publication date: May 8, 2025
    Inventors: Cheng-Ying HO, Kai-Chun HSU, Wen-De WANG, Yuh HUANG, Cheng-Yu HSIEH, Hung-Yu WANG, Jen-Cheng LIU
  • Publication number: 20250126914
    Abstract: An image sensor includes photosensitive areas in a first array within a semiconductor substrate. Microlens are disposed over the semiconductor substrate in a second array. Metal shields are disposed between a subset of the microlenses and corresponding photosensitive areas. The metal half-shields have dimensions and positions that provide half-shielding that enables half-shield phase detection autofocus. An antireflective coating is disposed over the metal half-shields. The metal half-shields and the antireflective coating may be in a composite grid that provides lateral separation between color filters. Alternatively, metal half-shields and the antireflective coating may be in below a layer that includes color filters. The antireflective coating includes a quarter-wave layer.
    Type: Application
    Filed: October 16, 2023
    Publication date: April 17, 2025
    Inventors: Cheng Ying Ho, Kai-Chun Hsu, Wen-De Wang, Cheng-Yu Hsieh, Jen-Cheng Liu
  • Patent number: 12249647
    Abstract: A power device includes a substrate, an ion well in the substrate, a body region in the ion well, a source doped region in the body region, a drain doped region in the ion well, and gates on the substrate between the source doped region and the drain doped region. The gates include a first gate adjacent to the source doped region, a second gate adjacent to the drain doped region, and a stacked gate structure between the first gate and the second gate.
    Type: Grant
    Filed: March 24, 2022
    Date of Patent: March 11, 2025
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chih-Chien Chang, Shen-De Wang, Cheng-Hua Yang, Linggang Fang, Jianjun Yang, Wei Ta
  • Patent number: 12230593
    Abstract: A package structure is provided, including a substrate, a first passivation layer, a metallization layer, a second passivation layer, and a polymer layer. The first passivation layer is formed over the substrate. The metallization layer is conformally formed on the first passivation layer. The second passivation layer is conformally formed on the first passivation layer and the metallization layer. A step structure is formed on the top surface of the second passivation layer, and includes at least one lower part that is lower than the other parts of the step structure. The polymer layer is formed over the second passivation layer. A portion of the polymer layer extends into the lower part of the step structure to engage with the step structure.
    Type: Grant
    Filed: July 30, 2021
    Date of Patent: February 18, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Kai-Heng Chen, Pei-Haw Tsao, Shyue-Ter Leu, Rung-De Wang, Chien-Chun Wang
  • Patent number: 12190767
    Abstract: A tiling device with a driving method having a low number of data pins is provided. The tiling device includes a first substrate, a second substrate and a data driving circuit. The first substrate includes a plurality of first semiconductor units. The second substrate includes a plurality of second semiconductor units. The data driving circuit simultaneously provides first data signals to the plurality of first semiconductor units and the plurality of second semiconductor units, and simultaneously provides second data signals to the plurality of first semiconductor units and the plurality of second semiconductor units.
    Type: Grant
    Filed: November 14, 2022
    Date of Patent: January 7, 2025
    Assignee: Innolux Corporation
    Inventors: Yu-Hsin Feng, Yu-Tse Lu, Chong-De Wang
  • Publication number: 20240429258
    Abstract: A process used to form a first deep trench isolation (DTI) structure in a pixel region of a semiconductor substrate is also used to form a second DTI structure in a guard ring area that isolates the pixel region from a peripheral region. The guard ring area may have a PNP guard ring structure. The second DTI structure may include trenches in each of an inner ring, a middle, and an outer ring of the PNP guard ring structure. The first and second DTI structures may have conductive cores. The conductive cores of the inner and outer ring may be biased to a first voltage while the conductive cores of the middle ring may be biased to an opposite polarity second voltage. When the second DTI structure have conductive cores with these biases, the second DTI structure may be used as the guard ring without the PNP structure.
    Type: Application
    Filed: June 26, 2023
    Publication date: December 26, 2024
    Inventors: Cheng-Ying Ho, Wen-De Wang, Kai-Chun Hsu, Yuh Ruey Huang, Chih-Lung Cheng, Jen-Cheng Liu
  • Publication number: 20240421177
    Abstract: Provided is a method of fabricating an image sensor device. An exemplary includes forming a plurality of radiation-sensing regions in a substrate. The substrate has a front surface, a back surface, and a sidewall that extends from the front surface to the back surface. The exemplary method further includes forming an interconnect structure over the front surface of the substrate, removing a portion of the substrate to expose a metal interconnect layer of the interconnect structure, and forming a bonding pad on the interconnect structure in a manner so that the bonding pad is electrically coupled to the exposed metal interconnect layer and separated from the sidewall of the substrate.
    Type: Application
    Filed: February 12, 2024
    Publication date: December 19, 2024
    Inventors: Shuang-Ji Tsai, Dun-Nian Yaung, Jen-Cheng Liu, Wen-De Wang, Hsiao-Hui Tseng
  • Patent number: 12154939
    Abstract: The present disclosure, in some embodiments, relates to a metal-insulator-metal (MIM) capacitor structure. The MIM capacitor structure includes one or more lower interconnects disposed within a lower dielectric structure over a substrate. A first dielectric layer is over the lower dielectric structure and includes sidewalls defining a plurality of openings extending through the first dielectric layer. A lower electrode is arranged along the sidewalls and over an upper surface of the first dielectric layer, a capacitor dielectric is arranged along sidewalls and an upper surface of the lower electrode, and an upper electrode is arranged along sidewalls and an upper surface of the capacitor dielectric. A spacer is along opposing outermost sidewalls of the upper electrode. The spacer has an outermost surface extending from a lowermost surface of the spacer to a top of the spacer. The outermost surface is substantially aligned with an outermost sidewall of the lower electrode.
    Type: Grant
    Filed: July 28, 2023
    Date of Patent: November 26, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ching-Sheng Chu, Dun-Nian Yaung, Yu-Cheng Tsai, Meng-Hsien Lin, Ching-Chung Su, Jen-Cheng Liu, Wen-De Wang, Guan-Hua Chen
  • Patent number: 12156487
    Abstract: A RRAM (resistive random-access memory) device includes a bottom electrode line, a top electrode island and a resistive material. The bottom electrode line is directly on a first metal structure. The top electrode island is disposed beside the bottom electrode line. The resistive material is sandwiched by a sidewall of the bottom electrode line and a sidewall of the top electrode island. The present invention also provides a method of forming the RRAM device.
    Type: Grant
    Filed: October 19, 2023
    Date of Patent: November 26, 2024
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chia-Ching Hsu, Wang Xiang, Shen-De Wang
  • Patent number: 12151452
    Abstract: The present invention relates to a composite laminate plate, a housing and a mobile communication device. The composite laminate includes a top metal layer with a through hole and an array antenna, and an area ratio of the array antenna to the through hole meets a specific range, thereby enhancing wave transmissivity of a millimeter wave. Moreover, the composite laminate has a specific material structure, such that it has good mechanical properties and low density. The housing and the mobile communication device made by the composite laminate have advantages of metallic texture, high signal intensity and excellent effect for light weight tendency.
    Type: Grant
    Filed: October 8, 2021
    Date of Patent: November 26, 2024
    Assignee: METAL INDUSTRIES RESEARCH & DEVELOPMENT CENTRE
    Inventors: Yen-Lin Huang, Pei-Jung Tsai, Li-De Wang, Chun-Chieh Wang
  • Publication number: 20240387613
    Abstract: The present disclosure, in some embodiments, relates to a capacitor structure. The capacitor structure includes one or more lower interconnects disposed within a lower dielectric structure over a substrate. A lower electrode is arranged along sidewalls and an upper surface of the lower dielectric structure, a capacitor dielectric is arranged along sidewalls and an upper surface of the lower electrode, and an upper electrode is arranged along sidewalls and an upper surface of the capacitor dielectric. A spacer is arranged along outermost sidewalls of the upper electrode. The spacer includes a first upper surface arranged along a first side of the upper electrode and a second upper surface arranged along an opposing second side of the upper electrode. The first upper surface has a different width than the second upper surface.
    Type: Application
    Filed: July 25, 2024
    Publication date: November 21, 2024
    Inventors: Ching-Sheng Chu, Dun-Nian Yaung, Yu-Cheng Tsai, Meng-Hsien Lin, Ching-Chung Su, Jen-Cheng Liu, Wen-De Wang, Guan-Hua Chen
  • Publication number: 20240321973
    Abstract: A power metal-oxide-semiconductor structure includes a semiconductor substrate, a gate electrode disposed above the semiconductor substrate, a field plate, and an electrically conductive pattern. The gate electrode and the field plate are disposed above the semiconductor substrate, the electrically conductive pattern is disposed between the field plate and the semiconductor substrate in a vertical direction, and the field plate and the electrically conductive pattern are located at the same side of the gate electrode in a horizontal direction. A manufacturing method of a power metal-oxide-semiconductor structure includes the following steps. The electrically conductive pattern and the field plate are formed above a first region of the semiconductor substrate. Subsequently, the gate electrode is formed above the first region of the semiconductor substrate.
    Type: Application
    Filed: April 24, 2023
    Publication date: September 26, 2024
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Cheng-Hua Yang, Chih-Chien CHANG, Shen-De WANG, JIANJUN YANG, Wei Ta, Yuan-Hsiang Chang
  • Publication number: 20240315017
    Abstract: A resistor between dummy flash structures includes a substrate. The substrate includes a resistor region and a flash region. A first dummy memory gate structure and a second dummy memory gate structure are disposed within the resistor region of the substrate. A polysilicon resistor is disposed between the first dummy memory gate structure and the second dummy memory gate structure. The polysilicon resistor contacts the first dummy memory gate structure and the second dummy memory gate structure.
    Type: Application
    Filed: April 17, 2023
    Publication date: September 19, 2024
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: WEICHANG LIU, Wang Xiang, CHIA CHING HSU, Yung-Lin Tseng, Shen-De Wang
  • Patent number: 12094395
    Abstract: An electronic device includes a gamma data source, a signal receiving circuit, a buffer circuit, a counter, a multiplexer, and a gamma processing unit. The signal receiving circuit receives source data, and correspondingly generates a grayscale value. The buffer circuit electrically couples the signal receiving circuit and stores the grayscale value. The counter receives a system clock signal to generate a sequence number. The multiplexer electrically couples the counter and the gamma data source. The multiplexer receives the sequence number. The multiplexer outputs a bit message corresponding to the sequence number in the gamma data source. The gamma processing unit electrically couples the multiplexer and the buffer circuit. The gamma processing unit receives the bit message from the multiplexer. The gamma processing unit receives the grayscale value from the buffer circuit. The gamma processing unit outputs a bit value corresponding to the grayscale value in the bit message.
    Type: Grant
    Filed: September 6, 2023
    Date of Patent: September 17, 2024
    Assignee: INNOLUX CORPORATION
    Inventors: Yu-Hsin Feng, Chong-De Wang, Yung-Hsin Chang
  • Publication number: 20240292765
    Abstract: A RRAM (resistive random-access memory) device includes a bottom electrode line directly on a first metal structure, a top electrode island disposed beside the bottom electrode line, a resistive material sandwiched by a sidewall of the bottom electrode line and a sidewall of the top electrode island, and a cap layer covering a portion of the first metal structure and under the bottom electrode line.
    Type: Application
    Filed: May 8, 2024
    Publication date: August 29, 2024
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Chia-Ching Hsu, Wang Xiang, Shen-De Wang
  • Patent number: 12010931
    Abstract: A RRAM (resistive random-access memory) device includes a bottom electrode line, a top electrode island and a resistive material. The bottom electrode line is directly on a first metal structure. The top electrode island is disposed beside the bottom electrode line. The resistive material is sandwiched by a sidewall of the bottom electrode line and a sidewall of the top electrode island. The present invention also provides a method of forming said RRAM device.
    Type: Grant
    Filed: March 9, 2021
    Date of Patent: June 11, 2024
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chia-Ching Hsu, Wang Xiang, Shen-De Wang
  • Patent number: 11990546
    Abstract: A semiconductor device includes a semiconductor substrate, a gate structure, a source region, a drain region, a first oxide layer, a field plate, and a second oxide layer. The gate structure is disposed on the semiconductor substrate. The source region and the drain region are disposed in the semiconductor substrate and located at two opposite sides of the gate structure respectively. The first oxide layer includes a first portion disposed between the gate structure and the semiconductor substrate and a second portion disposed between the gate structure and the drain region. The field plate is partly disposed above the gate structure and partly disposed above the second portion of the first oxide layer. The second oxide layer includes a first portion disposed between the field plate and the gate structure and a second portion disposed between the field plate and the second portion of the first oxide layer.
    Type: Grant
    Filed: March 13, 2023
    Date of Patent: May 21, 2024
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Cheng-Hua Yang, Chih-Chien Chang, Shen-De Wang
  • Publication number: 20240155843
    Abstract: A semiconductor device includes a substrate having a flash memory region and a logic device region, a logic transistor disposed in the logic device region, and a flash memory transistor disposed in the flash memory region. The flash memory transistor includes a metal select gate having two opposite sidewalls and two memory gates disposed on the two opposite sidewalls of the metal select gate.
    Type: Application
    Filed: November 28, 2022
    Publication date: May 9, 2024
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Wang Xiang, CHIA CHING HSU, Shen-De Wang, Yung-Lin Tseng, WEICHANG LIU
  • Publication number: 20240119888
    Abstract: An electronic device includes a gamma data source, a signal receiving circuit, a buffer circuit, a counter, a multiplexer, and a gamma processing unit. The signal receiving circuit receives source data, and correspondingly generates a grayscale value. The buffer circuit electrically couples the signal receiving circuit and stores the grayscale value. The counter receives a system clock signal to generate a sequence number. The multiplexer electrically couples the counter and the gamma data source. The multiplexer receives the sequence number. The multiplexer outputs a bit message corresponding to the sequence number in the gamma data source. The gamma processing unit electrically couples the multiplexer and the buffer circuit. The gamma processing unit receives the bit message from the multiplexer. The gamma processing unit receives the grayscale value from the buffer circuit. The gamma processing unit outputs a bit value corresponding to the grayscale value in the bit message.
    Type: Application
    Filed: September 6, 2023
    Publication date: April 11, 2024
    Inventors: Yu-Hsin FENG, Chong-De WANG, Yung-Hsin CHANG
  • Publication number: 20240081158
    Abstract: An RRAM structure includes a dielectric layer. A bottom electrode, a resistive switching layer and a top electrode are disposed from bottom to top on the dielectric layer. A spacer is disposed at sidewalls of the bottom electrode, the resistive switching layer and the top electrode. The spacer includes an L-shaped spacer and a sail-shaped spacer. The L-shaped spacer contacts the sidewall of the bottom electrode, the sidewall of the resistive switching layer and the sidewall of the top electrode. The sail-shaped spacer is disposed on the L-shaped spacer. A metal line is disposed on the top electrode and contacts the top electrode and the spacer.
    Type: Application
    Filed: September 21, 2022
    Publication date: March 7, 2024
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Wei Cheng, ZHEN CHEN, Shen-De Wang