Patents by Inventor De Wang

De Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • FinFET semiconductor device
    Patent number: 10332884
    Abstract: A method of manufacturing FinFET semiconductor devices in memory regions and logic regions includes the steps of forming a first gate material layer on a substrate and fins, patterning the first gate material layer to form a control gate, forming a second gate material layer on the substrate and fins, performing an etch process to the cell region so that the second gate material layer in the cell region is lower than the second gate material layer in the peripheral region, patterning the second gate material layer to form a select gate in the cell region and a dummy gate in the logic region respectively.
    Type: Grant
    Filed: November 2, 2017
    Date of Patent: June 25, 2019
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Liang Yi, Che-Jung Hsu, Yu-Cheng Tung, Jianjun Yang, Yuan-Hsiang Chang, Chih-Chien Chang, Weichang Liu, Shen-De Wang, Kok Wun Tan
  • Method for forming a semiconductor device
    Patent number: 10312249
    Abstract: A method for forming a semiconductor device is provided, including providing a substrate having a first area comprising first semiconductor structures and a second area, wherein one of the first semiconductor structures comprises a memory gate made of a first polysilicon layer, and a second semiconductor structure comprises a second polysilicon layer disposed within the second area on the substrate; forming an organic material layer on the first semiconductor structures within the first area and on the second polysilicon layer within the second area; and patterning the organic material layer to form a patterned organic material layer, and the organic material layer exposing the memory gates of the first semiconductor structures, wherein a first pre-determined region and a second pre-determined region at the substrate are covered by the patterned organic material layer.
    Type: Grant
    Filed: November 9, 2017
    Date of Patent: June 4, 2019
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Wei-Chang Liu, Zhen Chen, Shen-De Wang, Chuan Sun, Wei Ta, Wang Xiang
  • IMPACT ENERGY ABSORBING APPARATUS
    Publication number: 20190152415
    Abstract: An impact energy absorbing apparatus includes: a base, an axial crush component, a top plate, and an energy transfer component. The base is fastened to a protected object, and a tapered hole is provided on a top surface of the base. A bottom end face of the metal hollow rod of the axial crush component is joined with the top surface of the base. The energy transfer component includes a force bearing plate and a guiding rod extending outwards, where the force bearing plate is superimposed on a top surface of the metal hollow rod, the guiding rod is inserted to a position corresponding to the tapered hole in the metal hollow rod, an outer diameter of the guiding rod is less than a greatest diameter of the tapered hole, an inner diameter of the guiding rod is greater than a smallest diameter of the tapered hole.
    Type: Application
    Filed: November 20, 2018
    Publication date: May 23, 2019
    Inventors: PEI-CHUN TUNG, DIAN-YONG LIN, CHIN-KAI WANG, LI-DE WANG
  • Image sensor device and method of forming same
    Patent number: 10290671
    Abstract: An image sensor device includes a first substrate, an interconnect structure, a conductive layer, a conductive via and a second substrate. The first substrate includes a first region including a pixel array and a second region including a circuit. The interconnect structure is over the pixel array or the circuit. The interconnect structure electrically connecting the circuit to the pixel array. The conductive layer is on the interconnect structure. The conductive via passes through the second substrate and at least partially embedded in the conductive layer. The second substrate is over the conductive layer.
    Type: Grant
    Filed: September 25, 2017
    Date of Patent: May 14, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Wen-De Wang, Dun-Nian Yaung, Jen-Cheng Liu, Chun-Chieh Chuang, Jeng-Shyan Lin
  • METHOD FOR FORMING A SEMICONDUCTOR DEVICE
    Publication number: 20190139971
    Abstract: A method for forming a semiconductor device is provided, including providing a substrate having a first area comprising first semiconductor structures and a second area, wherein one of the first semiconductor structures comprises a memory gate made of a first polysilicon layer, and a second semiconductor structure comprises a second polysilicon layer disposed within the second area on the substrate; forming an organic material layer on the first semiconductor structures within the first area and on the second polysilicon layer within the second area; and patterning the organic material layer to form a patterned organic material layer, and the organic material layer exposing the memory gates of the first semiconductor structures, wherein a first pre-determined region and a second pre-determined region at the substrate are covered by the patterned organic material layer.
    Type: Application
    Filed: November 9, 2017
    Publication date: May 9, 2019
    Inventors: Wei-Chang LIU, Zhen CHEN, Shen-De WANG, Chuan SUN, Wei TA, Wang XIANG
  • SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF
    Publication number: 20190131251
    Abstract: A semiconductor structure includes a semiconductor device, a first seal ring, a second seal ring, and a plurality of through semiconductor vias (TSV). The semiconductor device has a first surface and a second surface opposite to the first surface. The first seal ring is disposed on the first surface of the semiconductor device and is adjacent to edges of the first surface. The second seal ring is disposed on the second surface of the semiconductor device and is adjacent to edges of the second surface. The TSVs penetrate through the semiconductor device and physically connect the first seal ring and the second seal ring.
    Type: Application
    Filed: January 10, 2018
    Publication date: May 2, 2019
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Rung-De Wang, Chen-Hsun Liu, Chin-Yu Ku, Te-Hsun Pang, Chia-Hua Wang, Pei-Shing Tsai, Po-Chang Lin
  • FINFET SEMICONDUCTOR DEVICE
    Publication number: 20190131302
    Abstract: A method of manufacturing FinFET semiconductor devices in memory regions and logic regions includes the steps of forming a first gate material layer on a substrate and fins, patterning the first gate material layer to form a control gate, forming a second gate material layer on the substrate and fins, performing an etch process to the cell region so that the second gate material layer in the cell region is lower than the second gate material layer in the peripheral region, patterning the second gate material layer to form a select gate in the cell region and a dummy gate in the logic region respectively.
    Type: Application
    Filed: November 2, 2017
    Publication date: May 2, 2019
    Inventors: Liang Yi, Che-Jung Hsu, Yu-Cheng Tung, JIANJUN YANG, Yuan-Hsiang Chang, Chih-Chien Chang, WEICHANG LIU, Shen-De Wang, KOK WUN TAN
  • Semiconductor structure and manufacturing method thereof
    Patent number: 10276514
    Abstract: A semiconductor structure includes a semiconductor device, a first seal ring, a second seal ring, and a plurality of through semiconductor vias (TSV). The semiconductor device has a first surface and a second surface opposite to the first surface. The first seal ring is disposed on the first surface of the semiconductor device and is adjacent to edges of the first surface. The second seal ring is disposed on the second surface of the semiconductor device and is adjacent to edges of the second surface. The TSVs penetrate through the semiconductor device and physically connect the first seal ring and the second seal ring.
    Type: Grant
    Filed: January 10, 2018
    Date of Patent: April 30, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Rung-De Wang, Chen-Hsun Liu, Chin-Yu Ku, Te-Hsun Pang, Chia-Hua Wang, Pei-Shing Tsai, Po-Chang Lin
  • Vertically Integrated Image Sensor Chips and Methods for Forming the Same
    Publication number: 20190123092
    Abstract: A method includes bonding a Backside Illumination (BSI) image sensor chip to a device chip, forming a first via in the BSI image sensor chip to connect to a first integrated circuit device in the BSI image sensor chip, forming a second via penetrating through the BSI image sensor chip to connect to a second integrated circuit device in the device chip, and forming a metal pad to connect the first via to the second via.
    Type: Application
    Filed: December 17, 2018
    Publication date: April 25, 2019
    Inventors: Jeng-Shyan Lin, Feng-Chi Hung, Dun-Nian Yaung, Jen-Cheng Liu, Szu-Ying Chen, Wen-De Wang, Tzu-Hsuan Hsu
  • SEAL RING STRUCTURES AND METHODS OF FORMING SAME
    Publication number: 20190109125
    Abstract: Some embodiments relate to a three-dimensional (3D) integrated circuit (IC). The 3D IC includes a first IC die comprising a first semiconductor substrate, and a first interconnect structure over the first semiconductor substrate. The 3D IC also includes a second IC die comprising a second semiconductor substrate, and a second interconnect structure that separates the second semiconductor substrate from the first interconnect structure. A seal ring structure separates the first interconnect structure from the second interconnect structure and perimetrically surrounds a gas reservoir between the first IC die and second IC die. The seal ring structure includes a sidewall gas-vent opening structure configured to allow gas to pass between the gas reservoir and an ambient environment surrounding the 3D IC.
    Type: Application
    Filed: November 27, 2018
    Publication date: April 11, 2019
    Inventors: Kuo-Ming Wu, Kuan-Liang Liu, Wen-De Wang, Yung-Lung Lin
  • Nonvolatile memory cell and fabrication method thereof
    Patent number: 10192874
    Abstract: A nonvolatile memory cell includes a substrate having a drain region, a source region, and a channel region between the drain region and the source region. A floating gate and a select gate are disposed on the channel region. A control gate is disposed on the floating gate. An erase gate is disposed on the source region. The erase gate includes a lower end portion that extends into a major surface of the substrate.
    Type: Grant
    Filed: June 19, 2017
    Date of Patent: January 29, 2019
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Liang Yi, Chih-Chien Chang, Shen-De Wang
  • NONVOLATILE MEMORY CELL AND FABRICATION METHOD THEREOF
    Publication number: 20180366478
    Abstract: A nonvolatile memory cell includes a substrate having a drain region, a source region, and a channel region between the drain region and the source region. A floating gate and a select gate are disposed on the channel region. A control gate is disposed on the floating gate. An erase gate is disposed on the source region. The erase gate includes a lower end portion that extends into a major surface of the substrate.
    Type: Application
    Filed: June 19, 2017
    Publication date: December 20, 2018
    Inventors: Liang Yi, Chih-Chien Chang, Shen-De Wang
  • Vertically integrated image sensor chips and methods for forming the same
    Patent number: 10157958
    Abstract: A method includes bonding a Backside Illumination (BSI) image sensor chip to a device chip, forming a first via in the BSI image sensor chip to connect to a first integrated circuit device in the BSI image sensor chip, forming a second via penetrating through the BSI image sensor chip to connect to a second integrated circuit device in the device chip, and forming a metal pad to connect the first via to the second via.
    Type: Grant
    Filed: December 18, 2017
    Date of Patent: December 18, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jeng-Shyan Lin, Feng-Chi Hung, Dun-Nian Yaung, Jen-Cheng Liu, Szu-Ying Chen, Wen-De Wang, Tzu-Hsuan Hsu
  • Semiconductor structure and method for forming the same
    Patent number: 10153359
    Abstract: A semiconductor structure and a method for forming the same are provided. The semiconductor structure comprises a substrate, at least a first cell, and at least a second cell. The substrate has a first region and a second region. The first and second cells are in the first and second regions respectively. The first cell comprises a first dielectric layer, a floating gate electrode, an oxide-nitride-oxide (ONO) gate dielectric layer, a second dielectric layer, and a control gate electrode. The ONO gate dielectric layer is on the floating gate electrode in the first dielectric layer on the substrate. The control gate electrode is in both of the first dielectric layer and the second dielectric layer on the first dielectric layer. The ONO gate dielectric layer contacting with the control gate electrode is wholly below a top surface of the first dielectric layer.
    Type: Grant
    Filed: August 11, 2016
    Date of Patent: December 11, 2018
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Liang Yi, Shen-De Wang
  • Isolation for semiconductor devices
    Patent number: 10128304
    Abstract: A system and method for isolating semiconductor devices is provided. An embodiment comprises an isolation region that is laterally removed from source/drain regions of semiconductor devices and has a dielectric material extending over the isolation implant between the source/drain regions. The isolation region may be formed by forming an opening through a layer over the substrate, depositing a dielectric material along the sidewalls of the opening, implanting ions into the substrate after the deposition, and filling the opening with another dielectric material.
    Type: Grant
    Filed: November 2, 2015
    Date of Patent: November 13, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wen-I Hsu, Min-Feng Kao, Jen-Cheng Liu, Dun-Nian Yaung, Tzu-Hsuan Hsu, Wen-De Wang
  • Method of manufacturing semiconductor memory device
    Patent number: 10121869
    Abstract: A method of manufacturing a semiconductor memory device and a semiconductor memory cell thereof are provided. The semiconductor memory device formed from the manufacturing method includes a plurality of semiconductor memory cells and an electric isolating structure. Each semiconductor memory cell includes a substrate, a first gate, a second gate, a first gate dielectric layer, a second gate dielectric layer, and a first spacing film. The first gate and the second gate are formed on the substrate. The first gate dielectric layer is between the first gate and the substrate, whereas the second gate dielectric layer is between the second gate and the substrate. The first spacing film having a side and a top edge is between the first gate and the second gate. The second gate covers the side and the top edge.
    Type: Grant
    Filed: December 5, 2017
    Date of Patent: November 6, 2018
    Assignee: UNITED MICROELECTRONICS CORPORATION
    Inventors: Weichang Liu, Zhen Chen, Shen-De Wang, Wang Xiang, Wei Ta
  • Semiconductor device having memory cell structure and method of manufacturing the same
    Patent number: 10090465
    Abstract: A semiconductor device is provided, including a lower conducting layer formed above a substrate, an upper conducting layer, and a memory cell structure formed on the lower conducting layer (such as formed between the lower and upper conducting layers). The memory cell structure includes a bottom electrode formed on the lower conducting layer and electrically connected to the lower conducting layer, a transitional metal oxide (TMO) layer formed on the bottom electrode, a TMO sidewall oxides formed at sidewalls of the TMO layer, a top electrode formed on the TMO layer, and spacers formed on the bottom electrode. The upper conducting layer is formed on the top electrode and electrically connected to the top electrode.
    Type: Grant
    Filed: November 23, 2016
    Date of Patent: October 2, 2018
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chia-Ching Hsu, Liang Yi, Shen-De Wang, Ko-Chi Chen
  • RESISTIVE RANDOM ACCESS MEMORY (RRAM) AND FORMING METHOD THEREOF
    Publication number: 20180205013
    Abstract: A method of forming a Resistive Random Access Memory (RRAM) includes the following steps. A first dielectric layer is formed on a first electrode layer. A second dielectric layer having a first trench is formed on the first dielectric layer. Spacers are formed beside sidewalls of the first trench. Apart of the first dielectric layer exposed by the spacers is removed, thereby forming a second trench in the first dielectric layer. A resistance switching material fills in the second trench. The second dielectric layer and the spacers are removed. A second electrode layer is formed on the resistance switching material and the first dielectric layer. The present invention also provides a RRAM formed by said method.
    Type: Application
    Filed: February 24, 2017
    Publication date: July 19, 2018
    Inventors: Liang Yi, Chia-Ching Hsu, Shen-De Wang, Ko-Chi Chen
  • Memory cell and manufacturing method thereof
    Patent number: 10020385
    Abstract: The present invention provides a memory cell, which includes a substrate, a gate dielectric layer, a patterned material layer, a selection gate and a control gate. The gate dielectric layer is disposed on the substrate. The patterned material layer is disposed on the substrate, wherein the patterned material layer comprises a vertical portion and a horizontal portion. The selection gate is disposed on the gate dielectric layer and atone side of the vertical portion of the patterned material layer. The control gate is disposed on the horizontal portion of the patterned material layer and at another side of the vertical portion, wherein the vertical portion protrudes over a top of the selection gate. The present invention further provides another embodiment of a memory cell and manufacturing methods thereof.
    Type: Grant
    Filed: March 19, 2014
    Date of Patent: July 10, 2018
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Yi-Shan Chiu, Shen-De Wang, Zhen Chen, Yuan-Hsiang Chang, Chih-Chien Chang, Jianjun Yang, Wei Ta
  • Implant isolated devices and method for forming the same
    Patent number: 10008532
    Abstract: A device includes a semiconductor substrate and implant isolation region extending from a top surface of the semiconductor substrate into the semiconductor substrate surrounding an active region. A gate dielectric is disposed over an active region of the semiconductor substrate and extends over the implant isolation region. A gate electrode is disposed over the gate dielectric and two end cap hardmasks are between the gate dielectric and the gate electrode over the implant isolation region. The two end cap hardmasks include same dopants as those implanted into the active region.
    Type: Grant
    Filed: April 21, 2016
    Date of Patent: June 26, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Min-Feng Kao, Dun-Nian Yaung, Jen-Cheng Liu, Tzu-Hsuan Hsu, Wen-De Wang, Wen-I Hsu